From f2dfef01e1fdf9d8218f0bc6ecfc3f943dc4d2a1 Mon Sep 17 00:00:00 2001 From: WANG Siyuan Date: Wed, 20 May 2015 14:41:01 +0800 Subject: southbridge/amd/pi: Add support for new AMD southbridge Kern Kern is the southbridge of AMD Merlin Falcon(Carrizo). This add support of HD audio, lpc, sata and usb for Kern. Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b Signed-off-by: WANG Siyuan Signed-off-by: WANG Siyuan Reviewed-on: http://review.coreboot.org/10418 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones Reviewed-by: Stefan Reinauer --- src/southbridge/amd/common/Makefile.inc | 1 + src/southbridge/amd/pi/Makefile.inc | 1 + src/southbridge/amd/pi/hudson/Kconfig | 13 ++- src/southbridge/amd/pi/hudson/Makefile.inc | 112 +++++++++++++++++++++- src/southbridge/amd/pi/hudson/acpi/pcie.asl | 8 ++ src/southbridge/amd/pi/hudson/acpi/usb.asl | 4 +- src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 5 + src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 4 + src/southbridge/amd/pi/hudson/hda.c | 7 +- src/southbridge/amd/pi/hudson/lpc.c | 8 +- src/southbridge/amd/pi/hudson/sata.c | 16 ++-- src/southbridge/amd/pi/hudson/usb.c | 34 ++----- 12 files changed, 174 insertions(+), 39 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc index 1f847cd0bb..50adf7b5fa 100644 --- a/src/southbridge/amd/common/Makefile.inc +++ b/src/southbridge/amd/common/Makefile.inc @@ -5,3 +5,4 @@ ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += amd_pci_util.c diff --git a/src/southbridge/amd/pi/Makefile.inc b/src/southbridge/amd/pi/Makefile.inc index f1e81ea011..b7a26562a3 100644 --- a/src/southbridge/amd/pi/Makefile.inc +++ b/src/southbridge/amd/pi/Makefile.inc @@ -18,3 +18,4 @@ # subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += hudson +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += hudson diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 7825b4d88a..36716fab0f 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -29,7 +29,13 @@ config SOUTHBRIDGE_AMD_PI_AVALON select HAVE_USBDEBUG_OPTIONS select HAVE_HARD_RESET -if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON +config SOUTHBRIDGE_AMD_PI_KERN + bool + select IOAPIC + select HAVE_USBDEBUG_OPTIONS + select HAVE_HARD_RESET + +if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN config BOOTBLOCK_SOUTHBRIDGE_INIT string @@ -79,16 +85,18 @@ config HUDSON_GEC_FWM config HUDSON_PSP bool - default y if CPU_AMD_PI_00730F01 + default y if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON + default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN depends on HUDSON_XHCI_FWM config HUDSON_IMC_FWM_FILE string "IMC firmware path and filename" default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON + default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN depends on HUDSON_IMC_FWM config HUDSON_GEC_FWM_FILE @@ -127,6 +135,7 @@ config AMD_PUBKEY_FILE depends on HUDSON_PSP string "AMD public Key" default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01 + default "3rdparty/blobs/southbridge/amd/kern/PSP/AmdPubKeyCZ.bin" if CPU_AMD_PI_00660F01 config HUDSON_SATA_MODE int "SATA Mode" diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c5978f1f55..5e8dbc23fc 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -99,6 +99,13 @@ HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE)),\ 65536) HUDSON_PSP_DIRECTORY_SIZE=256 +else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ + $(call int-add,\ + $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) $(XHCI_FWM_SIZE)\ + $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE)),\ + 65536) +HUDSON_PSP_DIRECTORY_SIZE=256 else HUDSON_PSP_DIRECTORY_POSITION=0 HUDSON_PSP_DIRECTORY_SIZE=0 @@ -172,48 +179,110 @@ FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE= endif +ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +FIRMWARE_TYPE=CZ +endif + +#5 CONFIG_PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key PUBSIGNEDKEY_POS=$(call int-align, \ $(call int-add,$(AMDPUBKEY_POS) $(AMDPUBKEY_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) PUBSIGNEDKEY_SIZE=$(call file-size,$(CONFIG_PUBSIGNEDKEY_FILE)) +#1 +ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader$(FIRMWARE_TYPE).Bypass.sbin +else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin +endif PSPBTLDR_POS=$(call int-align, \ $(call int-add,$(PUBSIGNEDKEY_POS) $(PUBSIGNEDKEY_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPBTLDR_SIZE=$(call file-size,$(CONFIG_PSPBTLDR_FILE)) +#3 +ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery$(FIRMWARE_TYPE).sbin +else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin +endif PSPRCVR_POS=$(call int-align, \ $(call int-add,$(PSPBTLDR_POS) $(PSPBTLDR_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPRCVR_SIZE=$(call file-size,$(CONFIG_PSPRCVR_FILE)) +#2 +ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs$(FIRMWARE_TYPE).sbin +else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).sbin +endif PSPSECUREOS_POS=$(call int-align, \ $(call int-add,$(PSPRCVR_POS) $(PSPRCVR_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPSECUREOS_SIZE=$(call file-size,$(CONFIG_PSPSCUREOS_FILE)) +#4 CONFIG_PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin PSPNVRAM_POS=$(call int-align, \ $(call int-add,$(PSPSECUREOS_POS) $(PSPSECUREOS_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPNVRAM_SIZE=$(call file-size,$(CONFIG_PSPNVRAM_FILE)) +#8 CONFIG_SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin SMUFWM_POS=$(call int-align, \ $(call int-add,$(PSPNVRAM_POS) $(PSPNVRAM_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUFWM_SIZE=$(call file-size,$(CONFIG_SMUFWM_FILE)) +#95 CONFIG_SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin SMUSCS_POS=$(call int-align, \ $(call int-add,$(SMUFWM_POS) $(SMUFWM_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUSCS_SIZE=$(call file-size,$(CONFIG_SMUSCS_FILE)) +#9 +CONFIG_PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +PSPSECUREDEBUG_POS=$(call int-align, \ + $(call int-add,$(SMUSCS_POS) $(SMUSCS_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +PSPSECUREDEBUG_SIZE=$(call file-size,$(CONFIG_PSPSECUREDEBUG_FILE)) + +#12 +ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) +CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_$(FIRMWARE_TYPE).cbin +endif +PSPTRUSTLETS_POS=$(call int-align, \ + $(call int-add,$(PSPSECUREDEBUG_POS) $(PSPSECUREDEBUG_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +PSPTRUSTLETS_SIZE=$(call file-size,$(CONFIG_PSPTRUSTLETS_FILE)) + +#13 +ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) +CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert +else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin +endif +TRUSTLETKEY_POS=$(call int-align, \ + $(call int-add,$(PSPTRUSTLETS_POS) $(PSPTRUSTLETS_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +TRUSTLETKEY_SIZE=$(call file-size,$(CONFIG_TRUSTLETKEY_FILE)) + +#18 +ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +CONFIG_SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin +SMUFIRMWARE2_POS=$(call int-align, \ + $(call int-add,$(TRUSTLETKEY_POS) $(TRUSTLETKEY_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +SMUFIRMWARE2_SIZE=$(call file-size,$(CONFIG_SMUFIRMWARE2_FILE)) +endif + define output_hex echo $(1) | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}' endef @@ -241,10 +310,24 @@ $(obj)/coreboot_psp_directory.bin: $(obj)/config.h $(FLETCHER) $(RTM_FILE) for fwm in 4 $(PSPNVRAM_SIZE) $(PSPNVRAM_POS) 0; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done >> $@_tail.tmp + for fwm in 9 $(PSPSECUREDEBUG_SIZE) $(PSPSECUREDEBUG_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $@_tail.tmp + for fwm in 12 $(PSPTRUSTLETS_SIZE) $(PSPTRUSTLETS_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $@_tail.tmp + for fwm in 13 $(TRUSTLETKEY_SIZE) $(TRUSTLETKEY_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $@_tail.tmp +ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) + for fwm in 18 $(SMUFIRMWARE2_SIZE) $(SMUFIRMWARE2_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $@_tail.tmp +endif for fwm in 95 $(SMUSCS_SIZE) $(SMUSCS_POS) 0; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done >> $@_tail.tmp - for fwm in 11 4294967295 0 0; do \ + for fwm in 11 4294967295 1 0; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done >> $@_tail.tmp for fwm in 1347637284 0 `ls -l $@_tail.tmp | awk '{printf("%d", $$5/16);}'` 0; do \ @@ -300,9 +383,36 @@ apu/smufwm-file := $(CONFIG_SMUFWM_FILE) apu/smufwm-position := $(SMUFWM_POS) apu/smufwm-type := raw +#95 cbfs-files-y += apu/smuscs apu/smuscs-file := $(CONFIG_SMUSCS_FILE) apu/smuscs-position := $(SMUSCS_POS) apu/smuscs-type := raw +#9 +cbfs-files-y += apu/pspsecuredebug +apu/pspsecuredebug-file := $(CONFIG_PSPSECUREDEBUG_FILE) +apu/pspsecuredebug-position := $(PSPSECUREDEBUG_POS) +apu/pspsecuredebug-type := raw + +#12 +cbfs-files-y += apu/psptrustlets +apu/psptrustlets-file := $(CONFIG_PSPTRUSTLETS_FILE) +apu/psptrustlets-position := $(PSPTRUSTLETS_POS) +apu/psptrustlets-type := raw + +#13 +cbfs-files-y += apu/trustletkey +apu/trustletkey-file := $(CONFIG_TRUSTLETKEY_FILE) +apu/trustletkey-position := $(TRUSTLETKEY_POS) +apu/trustletkey-type := raw + +#18 +ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +cbfs-files-y += apu/smufirmware2 +apu/smufirmware2-file := $(CONFIG_SMUFIRMWARE2_FILE) +apu/smufirmware2-position := $(SMUFIRMWARE2_POS) +apu/smufirmware2-type := raw +endif + endif diff --git a/src/southbridge/amd/pi/hudson/acpi/pcie.asl b/src/southbridge/amd/pi/hudson/acpi/pcie.asl index dbf4ccbd04..0626cab158 100644 --- a/src/southbridge/amd/pi/hudson/acpi/pcie.asl +++ b/src/southbridge/amd/pi/hudson/acpi/pcie.asl @@ -90,6 +90,14 @@ } IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x60), /* AcpiPm1EvgBlk */ + P1EB, 16, Offset(0xEE), UPWS, 3, } + OperationRegion (P1E0, SystemIO, P1EB, 0x04) + Field (P1E0, ByteAcc, Nolock, Preserve) { + Offset(0x02), + , 14, + PEWD, 1, + } diff --git a/src/southbridge/amd/pi/hudson/acpi/usb.asl b/src/southbridge/amd/pi/hudson/acpi/usb.asl index 453d792806..9b56985b1f 100644 --- a/src/southbridge/amd/pi/hudson/acpi/usb.asl +++ b/src/southbridge/amd/pi/hudson/acpi/usb.asl @@ -54,7 +54,7 @@ Device(UOH6) { Name(_PRW, Package() {0x0B, 3}) } /* end UOH5 */ -#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON +#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN /* 0:14.5 - OHCI */ Device(UEH1) { Name(_ADR, 0x00140005) @@ -68,7 +68,7 @@ Device(XHC0) { Name(_PRW, Package() {0x0B, 4}) } /* end XHC0 */ -#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON +#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN /* 0:10.1 - XHCI 1*/ Device(XHC1) { Name(_ADR, 0x00100001) diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 2ca91477df..a1e5e077c7 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -80,4 +80,9 @@ #define PIRQ_GPP3 0x53 /* GPP INT 3 */ #endif +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) +#define FCH_INT_TABLE_SIZE 0x75 +#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +#endif + #endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index ad26d63633..b48f87e204 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -33,6 +33,10 @@ const char * intr_types[] = { #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) [0x40] = "IDE\t", "SATA\t", [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) + [0x40] = "IDE\t", "SATA\t", + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", + [0x75] = NULL #endif }; diff --git a/src/southbridge/amd/pi/hudson/hda.c b/src/southbridge/amd/pi/hudson/hda.c index 3002dc565a..1eb77593ea 100644 --- a/src/southbridge/amd/pi/hudson/hda.c +++ b/src/southbridge/amd/pi/hudson/hda.c @@ -26,6 +26,11 @@ #include #include "hudson.h" +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_ATI_SB900_HDA, + PCI_DEVICE_ID_AMD_CZ_HDA, + 0 +}; static void hda_init(struct device *dev) { @@ -47,5 +52,5 @@ static struct device_operations hda_audio_ops = { static const struct pci_driver hdaaudio_driver __pci_driver = { .ops = &hda_audio_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_HDA, + .devices = pci_device_ids, }; diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index c727fa9fa1..2d1354cb3b 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -343,8 +343,14 @@ static struct device_operations lpc_ops = { .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_ATI_SB900_LPC, + PCI_DEVICE_ID_AMD_CZ_LPC, + 0 +}; static const struct pci_driver lpc_driver __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_LPC, + .devices = pci_device_ids, }; diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 8b8a79adce..1d2cd93724 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -29,7 +29,7 @@ static void sata_init(struct device *dev) { -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) /************************************** * Configure the SATA port multiplier * **************************************/ @@ -72,14 +72,16 @@ static struct device_operations sata_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_SATA, +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_ATI_SB900_SATA, + PCI_DEVICE_ID_ATI_SB900_SATA_AHCI, + PCI_DEVICE_ID_AMD_CZ_SATA, + PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + 0 }; -static const struct pci_driver sata0_driver_ahci __pci_driver = { +static const struct pci_driver sata0_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI, + .devices = pci_device_ids, }; diff --git a/src/southbridge/amd/pi/hudson/usb.c b/src/southbridge/amd/pi/hudson/usb.c index 6438be1583..f68652186a 100644 --- a/src/southbridge/amd/pi/hudson/usb.c +++ b/src/southbridge/amd/pi/hudson/usb.c @@ -43,35 +43,19 @@ static struct device_operations usb_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver usb_0_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_USB_18_0, +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_ATI_SB900_USB_18_0, + PCI_DEVICE_ID_ATI_SB900_USB_18_2, + PCI_DEVICE_ID_ATI_SB900_USB_20_5, + PCI_DEVICE_ID_AMD_CZ_USB_0, + PCI_DEVICE_ID_AMD_CZ_USB_1, + 0 }; -static const struct pci_driver usb_1_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_USB_18_2, -}; - -/* the pci id of usb ctrl 0 and 1 are the same. */ -/* - * static const struct pci_driver usb_3_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_AMD, - * .device = PCI_DEVICE_ID_ATI_HUDSON_USB_19_0, - * }; - * static const struct pci_driver usb_4_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_AMD, - * .device = PCI_DEVICE_ID_ATI_HUDSON_USB_19_1, - * }; - */ -static const struct pci_driver usb_4_driver __pci_driver = { +static const struct pci_driver usb_0_driver __pci_driver = { .ops = &usb_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_USB_20_5, + .devices = pci_device_ids, }; /* -- cgit v1.2.3