From 2e1fea408d8c7287497f0846715ee933fa9449f0 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Mon, 26 Nov 2018 10:33:00 +0100 Subject: superio: Add ASpeed AST2400 Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/common/conf_mode.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/superio/common') diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index dec630bfa4..8ba1cddba9 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Nico Huber + * Copyright (C) 2017-2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -48,6 +49,12 @@ void pnp_enter_conf_mode_a0a0(struct device *dev) outb(0xa0, dev->path.pnp.port); } +void pnp_enter_conf_mode_a5a5(struct device *dev) +{ + outb(0xa5, dev->path.pnp.port); + outb(0xa5, dev->path.pnp.port); +} + void pnp_exit_conf_mode_aa(struct device *dev) { outb(0xaa, dev->path.pnp.port); @@ -96,6 +103,11 @@ const struct pnp_mode_ops pnp_conf_mode_a0a0_aa = { .exit_conf_mode = pnp_exit_conf_mode_aa, }; +const struct pnp_mode_ops pnp_conf_mode_a5a5_aa = { + .enter_conf_mode = pnp_enter_conf_mode_a5a5, + .exit_conf_mode = pnp_exit_conf_mode_aa, +}; + const struct pnp_mode_ops pnp_conf_mode_870155_aa = { .enter_conf_mode = pnp_enter_conf_mode_870155aa, .exit_conf_mode = pnp_exit_conf_mode_0202, -- cgit v1.2.3