From 8301d8348a0848d56fdf4dbd76acd6bdcd3fc944 Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 07:07:33 +0000 Subject: second round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/superio/smsc/fdc37m60x/early_serial.c | 77 +++++++++++++ .../smsc/fdc37m60x/fdc37m60x_early_serial.c | 77 ------------- src/superio/smsc/lpc47b272/early_serial.c | 53 +++++++++ .../smsc/lpc47b272/lpc47b272_early_serial.c | 53 --------- src/superio/smsc/lpc47b397/early_gpio.c | 49 ++++++++ src/superio/smsc/lpc47b397/early_serial.c | 46 ++++++++ src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c | 49 -------- .../smsc/lpc47b397/lpc47b397_early_serial.c | 46 -------- src/superio/smsc/lpc47m10x/early_serial.c | 51 +++++++++ .../smsc/lpc47m10x/lpc47m10x_early_serial.c | 51 --------- src/superio/smsc/lpc47m15x/early_serial.c | 45 ++++++++ .../smsc/lpc47m15x/lpc47m15x_early_serial.c | 45 -------- src/superio/smsc/lpc47n217/early_serial.c | 123 +++++++++++++++++++++ .../smsc/lpc47n217/lpc47n217_early_serial.c | 123 --------------------- src/superio/smsc/lpc47n227/early_serial.c | 122 ++++++++++++++++++++ .../smsc/lpc47n227/lpc47n227_early_serial.c | 122 -------------------- src/superio/smsc/smscsuperio/early_serial.c | 46 ++++++++ .../smsc/smscsuperio/smscsuperio_early_serial.c | 46 -------- 18 files changed, 612 insertions(+), 612 deletions(-) create mode 100644 src/superio/smsc/fdc37m60x/early_serial.c delete mode 100644 src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c create mode 100644 src/superio/smsc/lpc47b272/early_serial.c delete mode 100644 src/superio/smsc/lpc47b272/lpc47b272_early_serial.c create mode 100644 src/superio/smsc/lpc47b397/early_gpio.c create mode 100644 src/superio/smsc/lpc47b397/early_serial.c delete mode 100644 src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c delete mode 100644 src/superio/smsc/lpc47b397/lpc47b397_early_serial.c create mode 100644 src/superio/smsc/lpc47m10x/early_serial.c delete mode 100644 src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c create mode 100644 src/superio/smsc/lpc47m15x/early_serial.c delete mode 100644 src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c create mode 100644 src/superio/smsc/lpc47n217/early_serial.c delete mode 100644 src/superio/smsc/lpc47n217/lpc47n217_early_serial.c create mode 100644 src/superio/smsc/lpc47n227/early_serial.c delete mode 100644 src/superio/smsc/lpc47n227/lpc47n227_early_serial.c create mode 100644 src/superio/smsc/smscsuperio/early_serial.c delete mode 100644 src/superio/smsc/smscsuperio/smscsuperio_early_serial.c (limited to 'src/superio/smsc') diff --git a/src/superio/smsc/fdc37m60x/early_serial.c b/src/superio/smsc/fdc37m60x/early_serial.c new file mode 100644 index 0000000000..d8cd8c683d --- /dev/null +++ b/src/superio/smsc/fdc37m60x/early_serial.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "fdc37m60x.h" + +/* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */ +#define SIO_BASE 0x3f0 +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */ +#define FDC37M60X_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define FDC37M60X_CONFIG_POWER_CONTROL 0x22 /* Power Control. */ +#define FDC37M60X_CONFIG_POWER_MGMT 0x23 /* Intelligent Power Mgmt. */ +#define FDC37M60X_CONFIG_OSC 0x24 /* OSC. */ + +#define FDC37M60X_CONFIGURATION_PORT 0x3f0 /* Write-only. */ + +/* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the + LDN the register belongs to, before you can access the register. */ +static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value) +{ + outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +/* Enable the peripheral devices on the FDC37M60X Super I/O chip. */ +static void fdc37m60x_enable_serial(device_t dev, u16 iobase) +{ + /* (1) Enter the configuration state. */ + outb(0x55, FDC37M60X_CONFIGURATION_PORT); + + /* (2) Modify the data of configuration registers. */ + + /* Power on all devices by setting the respective bit. + Bits: 0 (FDC), 3 (PP), 4 (Com1), 5 (Com2). The rest is reserved. */ + fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_CONTROL, 0x39); + + /* Disable intelligent power management. */ + fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_MGMT, 0x00); + + /* Turn on OSC, turn on BRG clock. */ + fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_OSC, 0x04); + + /* Configure serial port 1. */ + fdc37m60x_sio_write(FDC37M60X_SP1, 0x60, 0x03); + fdc37m60x_sio_write(FDC37M60X_SP1, 0x61, 0xf8); /* I/O 0x3f8 */ + fdc37m60x_sio_write(FDC37M60X_SP1, 0x70, 0x04); /* IRQ 4 */ + fdc37m60x_sio_write(FDC37M60X_SP1, 0xf0, 0x00); /* Normal */ + + /* Enable serial port 1. */ + fdc37m60x_sio_write(FDC37M60X_SP1, 0x30, 0x01); + + /* (3) Exit the configuration state. */ + outb(0xaa, FDC37M60X_CONFIGURATION_PORT); +} diff --git a/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c b/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c deleted file mode 100644 index d8cd8c683d..0000000000 --- a/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "fdc37m60x.h" - -/* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */ -#define SIO_BASE 0x3f0 -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */ -#define FDC37M60X_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define FDC37M60X_CONFIG_POWER_CONTROL 0x22 /* Power Control. */ -#define FDC37M60X_CONFIG_POWER_MGMT 0x23 /* Intelligent Power Mgmt. */ -#define FDC37M60X_CONFIG_OSC 0x24 /* OSC. */ - -#define FDC37M60X_CONFIGURATION_PORT 0x3f0 /* Write-only. */ - -/* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value) -{ - outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -/* Enable the peripheral devices on the FDC37M60X Super I/O chip. */ -static void fdc37m60x_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state. */ - outb(0x55, FDC37M60X_CONFIGURATION_PORT); - - /* (2) Modify the data of configuration registers. */ - - /* Power on all devices by setting the respective bit. - Bits: 0 (FDC), 3 (PP), 4 (Com1), 5 (Com2). The rest is reserved. */ - fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_CONTROL, 0x39); - - /* Disable intelligent power management. */ - fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_MGMT, 0x00); - - /* Turn on OSC, turn on BRG clock. */ - fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_OSC, 0x04); - - /* Configure serial port 1. */ - fdc37m60x_sio_write(FDC37M60X_SP1, 0x60, 0x03); - fdc37m60x_sio_write(FDC37M60X_SP1, 0x61, 0xf8); /* I/O 0x3f8 */ - fdc37m60x_sio_write(FDC37M60X_SP1, 0x70, 0x04); /* IRQ 4 */ - fdc37m60x_sio_write(FDC37M60X_SP1, 0xf0, 0x00); /* Normal */ - - /* Enable serial port 1. */ - fdc37m60x_sio_write(FDC37M60X_SP1, 0x30, 0x01); - - /* (3) Exit the configuration state. */ - outb(0xaa, FDC37M60X_CONFIGURATION_PORT); -} diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c new file mode 100644 index 0000000000..75093ea0a9 --- /dev/null +++ b/src/superio/smsc/lpc47b272/early_serial.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Digital Design Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */ + +#include +#include "lpc47b272.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Processor I/O port address to assign to this serial device. + */ +static void lpc47b272_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c b/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c deleted file mode 100644 index 75093ea0a9..0000000000 --- a/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */ - -#include -#include "lpc47b272.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/** - * Configure the base I/O port of the specified serial device and enable the - * serial device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Processor I/O port address to assign to this serial device. - */ -static void lpc47b272_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47b397/early_gpio.c b/src/superio/smsc/lpc47b397/early_gpio.c new file mode 100644 index 0000000000..16066b75cd --- /dev/null +++ b/src/superio/smsc/lpc47b397/early_gpio.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static void lpc47b397_gpio_offset_out(u16 iobase, u16 offset, u8 value) +{ + outb(value, iobase + offset); +} + +static u8 lpc47b397_gpio_offset_in(u16 iobase, u16 offset) +{ + return inb(iobase+offset); +} + +#if 0 +/* For GP60-GP64, GP66-GP85. */ +#define LPC47B397_GPIO_CNTL_INDEX 0x70 +#define LPC47B397_GPIO_CNTL_DATA 0x71 + +static void lpc47b397_gpio_index_out(u16 iobase, u8 index, u8 value) +{ + outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); + outb(value, iobase + LPC47B397_GPIO_CNTL_DATA); +} + +static u8 lpc47b397_gpio_index_in(u16 iobase, u8 index) +{ + outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); + return inb(iobase + LPC47B397_GPIO_CNTL_DATA); +} +#endif diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c new file mode 100644 index 0000000000..bea97b45f7 --- /dev/null +++ b/src/superio/smsc/lpc47b397/early_serial.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "lpc47b397.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void lpc47b397_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c b/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c deleted file mode 100644 index 16066b75cd..0000000000 --- a/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -static void lpc47b397_gpio_offset_out(u16 iobase, u16 offset, u8 value) -{ - outb(value, iobase + offset); -} - -static u8 lpc47b397_gpio_offset_in(u16 iobase, u16 offset) -{ - return inb(iobase+offset); -} - -#if 0 -/* For GP60-GP64, GP66-GP85. */ -#define LPC47B397_GPIO_CNTL_INDEX 0x70 -#define LPC47B397_GPIO_CNTL_DATA 0x71 - -static void lpc47b397_gpio_index_out(u16 iobase, u8 index, u8 value) -{ - outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); - outb(value, iobase + LPC47B397_GPIO_CNTL_DATA); -} - -static u8 lpc47b397_gpio_index_in(u16 iobase, u8 index) -{ - outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); - return inb(iobase + LPC47B397_GPIO_CNTL_DATA); -} -#endif diff --git a/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c b/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c deleted file mode 100644 index bea97b45f7..0000000000 --- a/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "lpc47b397.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void lpc47b397_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c new file mode 100644 index 0000000000..06cf7d4030 --- /dev/null +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Digital Design Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "lpc47m10x.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Processor I/O port address to assign to this serial device. + */ +static void lpc47m10x_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c b/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c deleted file mode 100644 index 06cf7d4030..0000000000 --- a/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "lpc47m10x.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/** - * Configure the base I/O port of the specified serial device and enable the - * serial device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Processor I/O port address to assign to this serial device. - */ -static void lpc47m10x_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c new file mode 100644 index 0000000000..bc417d86ef --- /dev/null +++ b/src/superio/smsc/lpc47m15x/early_serial.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */ + +#include +#include "lpc47m15x.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static inline void lpc47m15x_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c b/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c deleted file mode 100644 index bc417d86ef..0000000000 --- a/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */ - -#include -#include "lpc47m15x.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static inline void lpc47m15x_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c new file mode 100644 index 0000000000..ce79db8f0c --- /dev/null +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Digital Design Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */ + +#include +#include +#include "lpc47n217.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +/** + * Program the base I/O port for the specified logical device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Base I/O port for the logical device. + */ +void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) +{ + /* LPC47N217 requires base ports to be a multiple of 4. */ + ASSERT(!(iobase & 0x3)); + + switch(dev & 0xFF) { + case LPC47N217_PP: + pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); + break; + case LPC47N217_SP1: + pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); + break; + case LPC47N217_SP2: + pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); + break; + default: + break; + } +} + +/** + * Enable or disable the specified logical device. + * + * Technically, a full disable requires setting the device's base I/O port + * below 0x100. We don't do that here, because we don't have access to a data + * structure that specifies what the 'real' base port is (when asked to enable + * the device). Also the function is used only to disable the device while its + * true base port is programmed (see lpc47n217_enable_serial() below). + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param enable 0 to disable, anythig else to enable. + */ +void lpc47n217_pnp_set_enable(device_t dev, int enable) +{ + u8 power_register = 0, power_mask = 0, current_power, new_power; + + switch(dev & 0xFF) { + case LPC47N217_PP: + power_register = 0x01; + power_mask = 0x04; + break; + case LPC47N217_SP1: + power_register = 0x02; + power_mask = 0x08; + break; + case LPC47N217_SP2: + power_register = 0x02; + power_mask = 0x80; + break; + default: + return; + } + + current_power = pnp_read_config(dev, power_register); + new_power = current_power & ~power_mask; /* Disable by default. */ + if (enable) + new_power |= power_mask; /* Enable. */ + pnp_write_config(dev, power_register, new_power); +} + +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Processor I/O port address to assign to this serial device. + */ +static void lpc47n217_enable_serial(device_t dev, u16 iobase) +{ + /* + * NOTE: Cannot use pnp_set_XXX() here because they assume chip + * support for logical devices, which the LPC47N217 doesn't have. + */ + pnp_enter_conf_state(dev); + lpc47n217_pnp_set_enable(dev, 0); + lpc47n217_pnp_set_iobase(dev, iobase); + lpc47n217_pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c b/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c deleted file mode 100644 index ce79db8f0c..0000000000 --- a/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */ - -#include -#include -#include "lpc47n217.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/** - * Program the base I/O port for the specified logical device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Base I/O port for the logical device. - */ -void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) -{ - /* LPC47N217 requires base ports to be a multiple of 4. */ - ASSERT(!(iobase & 0x3)); - - switch(dev & 0xFF) { - case LPC47N217_PP: - pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); - break; - case LPC47N217_SP1: - pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); - break; - case LPC47N217_SP2: - pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); - break; - default: - break; - } -} - -/** - * Enable or disable the specified logical device. - * - * Technically, a full disable requires setting the device's base I/O port - * below 0x100. We don't do that here, because we don't have access to a data - * structure that specifies what the 'real' base port is (when asked to enable - * the device). Also the function is used only to disable the device while its - * true base port is programmed (see lpc47n217_enable_serial() below). - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param enable 0 to disable, anythig else to enable. - */ -void lpc47n217_pnp_set_enable(device_t dev, int enable) -{ - u8 power_register = 0, power_mask = 0, current_power, new_power; - - switch(dev & 0xFF) { - case LPC47N217_PP: - power_register = 0x01; - power_mask = 0x04; - break; - case LPC47N217_SP1: - power_register = 0x02; - power_mask = 0x08; - break; - case LPC47N217_SP2: - power_register = 0x02; - power_mask = 0x80; - break; - default: - return; - } - - current_power = pnp_read_config(dev, power_register); - new_power = current_power & ~power_mask; /* Disable by default. */ - if (enable) - new_power |= power_mask; /* Enable. */ - pnp_write_config(dev, power_register, new_power); -} - -/** - * Configure the base I/O port of the specified serial device and enable the - * serial device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Processor I/O port address to assign to this serial device. - */ -static void lpc47n217_enable_serial(device_t dev, u16 iobase) -{ - /* - * NOTE: Cannot use pnp_set_XXX() here because they assume chip - * support for logical devices, which the LPC47N217 doesn't have. - */ - pnp_enter_conf_state(dev); - lpc47n217_pnp_set_enable(dev, 0); - lpc47n217_pnp_set_iobase(dev, iobase); - lpc47n217_pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c new file mode 100644 index 0000000000..32bd3e3680 --- /dev/null +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Digital Design Corporation + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */ + +#include +#include "lpc47n227.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +/** + * Program the base I/O port for the specified logical device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Base I/O port for the logical device. + */ +void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) +{ + /* LPC47N227 requires base ports to be a multiple of 4. */ + ASSERT(!(iobase & 0x3)); + + switch (dev & 0xFF) { + case LPC47N227_PP: + pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); + break; + case LPC47N227_SP1: + pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); + break; + case LPC47N227_SP2: + pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); + break; + default: + break; + } +} + +/** + * Enable or disable the specified logical device. + * + * Technically, a full disable requires setting the device's base I/O port + * below 0x100. We don't do that here, because we don't have access to a data + * structure that specifies what the 'real' base port is (when asked to enable + * the device). Also the function is used only to disable the device while its + * true base port is programmed (see lpc47n227_enable_serial() below). + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param enable 0 to disable, anythig else to enable. + */ +void lpc47n227_pnp_set_enable(device_t dev, int enable) +{ + u8 power_register = 0, power_mask = 0, current_power, new_power; + + switch (dev & 0xFF) { + case LPC47N227_PP: + power_register = 0x01; + power_mask = 0x04; + break; + case LPC47N227_SP1: + power_register = 0x02; + power_mask = 0x08; + break; + case LPC47N227_SP2: + power_register = 0x02; + power_mask = 0x80; + break; + default: + return; + } + + current_power = pnp_read_config(dev, power_register); + new_power = current_power & ~power_mask; /* Disable by default. */ + if (enable) + new_power |= power_mask; /* Enable. */ + pnp_write_config(dev, power_register, new_power); +} + +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Processor I/O port address to assign to this serial device. + */ +static void lpc47n227_enable_serial(device_t dev, u16 iobase) +{ + /* + * NOTE: Cannot use pnp_set_XXX() here because they assume chip + * support for logical devices, which the LPC47N227 doesn't have. + */ + pnp_enter_conf_state(dev); + lpc47n227_pnp_set_enable(dev, 0); + lpc47n227_pnp_set_iobase(dev, iobase); + lpc47n227_pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c b/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c deleted file mode 100644 index 32bd3e3680..0000000000 --- a/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */ - -#include -#include "lpc47n227.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/** - * Program the base I/O port for the specified logical device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Base I/O port for the logical device. - */ -void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) -{ - /* LPC47N227 requires base ports to be a multiple of 4. */ - ASSERT(!(iobase & 0x3)); - - switch (dev & 0xFF) { - case LPC47N227_PP: - pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); - break; - case LPC47N227_SP1: - pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); - break; - case LPC47N227_SP2: - pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); - break; - default: - break; - } -} - -/** - * Enable or disable the specified logical device. - * - * Technically, a full disable requires setting the device's base I/O port - * below 0x100. We don't do that here, because we don't have access to a data - * structure that specifies what the 'real' base port is (when asked to enable - * the device). Also the function is used only to disable the device while its - * true base port is programmed (see lpc47n227_enable_serial() below). - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param enable 0 to disable, anythig else to enable. - */ -void lpc47n227_pnp_set_enable(device_t dev, int enable) -{ - u8 power_register = 0, power_mask = 0, current_power, new_power; - - switch (dev & 0xFF) { - case LPC47N227_PP: - power_register = 0x01; - power_mask = 0x04; - break; - case LPC47N227_SP1: - power_register = 0x02; - power_mask = 0x08; - break; - case LPC47N227_SP2: - power_register = 0x02; - power_mask = 0x80; - break; - default: - return; - } - - current_power = pnp_read_config(dev, power_register); - new_power = current_power & ~power_mask; /* Disable by default. */ - if (enable) - new_power |= power_mask; /* Enable. */ - pnp_write_config(dev, power_register, new_power); -} - -/** - * Configure the base I/O port of the specified serial device and enable the - * serial device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Processor I/O port address to assign to this serial device. - */ -static void lpc47n227_enable_serial(device_t dev, u16 iobase) -{ - /* - * NOTE: Cannot use pnp_set_XXX() here because they assume chip - * support for logical devices, which the LPC47N227 doesn't have. - */ - pnp_enter_conf_state(dev); - lpc47n227_pnp_set_enable(dev, 0); - lpc47n227_pnp_set_iobase(dev, iobase); - lpc47n227_pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c new file mode 100644 index 0000000000..281a35c861 --- /dev/null +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +/* All known/supported SMSC Super I/Os have the same logical device IDs + * for the serial ports (COM1, COM2). + */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ + +/** + * Enable the specified serial port. + * + * @param dev The device to use. + * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). + */ +static inline void smscsuperio_enable_serial(device_t dev, u16 iobase) +{ + u16 port = dev >> 8; + + outb(0x55, port); /* Enter the configuration state. */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + outb(0xaa, port); /* Exit the configuration state. */ +} diff --git a/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c b/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c deleted file mode 100644 index 281a35c861..0000000000 --- a/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include - -/* All known/supported SMSC Super I/Os have the same logical device IDs - * for the serial ports (COM1, COM2). - */ -#define SMSCSUPERIO_SP1 4 /* Com1 */ -#define SMSCSUPERIO_SP2 5 /* Com2 */ - -/** - * Enable the specified serial port. - * - * @param dev The device to use. - * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). - */ -static inline void smscsuperio_enable_serial(device_t dev, u16 iobase) -{ - u16 port = dev >> 8; - - outb(0x55, port); /* Enter the configuration state. */ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - outb(0xaa, port); /* Exit the configuration state. */ -} -- cgit v1.2.3