From 13df640bf7a9b7e402fd4d3082415ab65ef45057 Mon Sep 17 00:00:00 2001 From: Anish K Patel Date: Sun, 14 Feb 2010 16:13:03 +0000 Subject: Add w83627hf_set_clksel_48() function which sets CLKSEL to 48MHz. The Win Ent platforms are using the Winbond W83627HG part, but this part does not appear to enable 48MHz clock by default as claimed in the datasheet. Signed-off-by: Anish K Patel Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/superio/winbond/w83627hf/w83627hf_early_serial.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/superio/winbond') diff --git a/src/superio/winbond/w83627hf/w83627hf_early_serial.c b/src/superio/winbond/w83627hf/w83627hf_early_serial.c index cc0bf1cfe4..e4b49d1eee 100644 --- a/src/superio/winbond/w83627hf/w83627hf_early_serial.c +++ b/src/superio/winbond/w83627hf/w83627hf_early_serial.c @@ -45,3 +45,13 @@ static void w83627hf_enable_serial(device_t dev, unsigned iobase) pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } + +static void w83627hf_set_clksel_48(device_t dev) +{ + unsigned port = dev >> 8; + pnp_enter_ext_func_mode(dev); + outb(0x24, port); + /* Set CLKSEL (clock input on pin 1) to 48MHz. */ + outb(inb(port + 1) | (1 << 6), port + 1); + pnp_exit_ext_func_mode(dev); +} -- cgit v1.2.3