From 7d94cf93eec15dfb8eef9cd044fe39319d4ee9bc Mon Sep 17 00:00:00 2001 From: zbao Date: Mon, 2 Jul 2012 14:19:14 +0800 Subject: AGESA F15tn: AMD family15 AGESA code for Trinity AMD AGESA code for trinity. Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592 Signed-off-by: Zheng Bao Signed-off-by: zbao Reviewed-on: http://review.coreboot.org/1155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c | 122 +++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c (limited to 'src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c') diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c new file mode 100644 index 0000000000..8c154a5fa1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c @@ -0,0 +1,122 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch LPC controller + * + * Init LPC Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. 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Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_SPI_LPCENV_FILECODE + + + +/** + * FchInitEnvLpc - Config LPC controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvLpc ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + // LPC CFG programming + // + // + // Turn on and configure LPC clock (48MHz) + // + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x28, AccessWidth32, (UINT32)~(BIT21 + BIT20 + BIT19), 2 << 19); + RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT7, 0); + + // + // Initialization of pci config space + // + FchInitEnvLpcProgram (FchDataPtr); + + // + // SSID for LPC Controller + // + if (LocalCfgPtr->Spi.LpcSsid != 0 ) { + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Spi.LpcSsid, StdHeader); + } + // + // LPC MSI + // + if ( LocalCfgPtr->Spi.LpcMsiEnable ) { + RwPci ((LPC_BUS_DEV_FUN << 16) + 0x78 , AccessWidth32, (UINT32)~BIT1, (UINT32)BIT1, StdHeader); + } +} + -- cgit v1.2.3