From fec6fa799ce16eabec0add9bfe6ab5222921f612 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 12 Jul 2017 16:30:47 +0300 Subject: vendorcode/amd/agesa: Tidy up gcccar.inc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change register preservations and fix comments about register usage accordingly. Do this to avoid use of %mm0-2 registers inside macros defined in gcccar.inc, as future implementation of C_BOOTBLOCK_ENVIRONMENT will use them as well. Adjust caller side accordingly. Change-Id: Ic76fcc31ae714baf5259d17c41b62a3610aa947b Signed-off-by: Marshall Dawson Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/20579 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/vendorcode/amd/agesa/f15tn/gcccar.inc | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) (limited to 'src/vendorcode/amd/agesa/f15tn') diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index 4f1e7a0b25..7ac9613fca 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1511,7 +1511,7 @@ node_core_f15_exit: * AMD_ENABLE_STACK: Setup a stack * * In: -* EBX = Return address (preserved) +* No inputs * * Out: * SS:ESP - Our new private stack location @@ -1522,11 +1522,8 @@ node_core_f15_exit: * * Requirements: * * This routine presently is limited to a max of 64 processor cores -* Preserved: -* ebx ebp * Destroyed: -* eax, ecx, edx, edi, esi, ds, es, ss, esp -* mmx0, mmx1 +* EBX, EDX, EDI, ESI, EBP, DS, ES * * Description: * Fixed MTRR address allocation to cores: @@ -1586,8 +1583,6 @@ node_core_f15_exit: # Note that SS:ESP will be default stack. Note that this stack # routine will not be used after memory has been initialized. Because # of its limited lifetime, it will not conflict with typical PCI devices. - movd %ebx, %mm0 # Put return address in a safe place - movd %ebp, %mm1 # Save some other user registers # get node id and core id of current executing core GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node) @@ -1899,9 +1894,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up) #.endif 0: - - movd %mm0, %ebx # Restore return address - movd %mm1, %ebp .endm /***************************************************************************** @@ -1921,17 +1913,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is * none * * Out: -* EAX = AGESA_SUCCESS +* none * * Preserved: -* ebx +* ESP * Destroyed: -* eax, ecx, edx, esp +* EAX, EBX, ECX, EDX, EDI, ESI *****************************************************************************/ .macro AMD_DISABLE_STACK - mov %ebx, %esp # Save return address - # get node/core/flags of current executing core GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) @@ -1957,7 +1947,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations - mov %esp, %ebx - xor %eax, %eax - .endm -- cgit v1.2.3