From d844431af09aafd65656f77b699c737966b30086 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 10 Jun 2019 13:47:56 +0200 Subject: vendorcode/agesa: Fix check for valid PhyLane MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Found using GCC with flag -Wlogical-op Change-Id: Ia04ac5b1d0a4434c0ab2ca583b9b03dbfd0ffd41 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/33362 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c | 2 +- .../amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c | 2 +- .../amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c | 2 +- .../amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/vendorcode/amd/agesa') diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c index ee7ef01035..c76b290727 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -202,7 +202,7 @@ PcieConfigGetNumberOfPhyLane ( IN PCIe_ENGINE_CONFIG *Engine ) { - if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) { + if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) { return 0; } if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c index 788c0b779a..dae9899683 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -178,7 +178,7 @@ PcieConfigGetNumberOfPhyLane ( IN PCIe_ENGINE_CONFIG *Engine ) { - if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) { + if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) { return 0; } if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c index 6466862194..9b7bcbded2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -205,7 +205,7 @@ PcieConfigGetNumberOfPhyLane ( IN PCIe_ENGINE_CONFIG *Engine ) { - if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) { + if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) { return 0; } if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) { diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c index 8e5e3dd43a..27e7bcefda 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -205,7 +205,7 @@ PcieConfigGetNumberOfPhyLane ( IN PCIe_ENGINE_CONFIG *Engine ) { - if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) { + if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.EndLane >= UNUSED_LANE_ID) { return 0; } if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) { -- cgit v1.2.3