From 083379d0f8a8524c4ffc708350c3e2c9fae683af Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Wed, 1 Apr 2020 15:56:11 -0700 Subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527 Update FSP headers for Tiger Lake platform generated based FSP version 2527. Which includes below additional UPDs: FSPM: - PchTraceHubMode - CpuTraceHubMode - CpuPcieRpEnableMask FSPS: - D3HotEnable - D3ColdEnable - RtcMemoryLock - PchLockDownGlobalSmi - PchLockDownBiosInterface - PchUnlockGpioPads - CpuMpPpi - ThcPort0Assignment - ThcPort1Assignment BUG=b:150357377 BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40026 Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h | 2 +- .../intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 104 +++++++++++------ .../intel/fsp/fsp2_0/tigerlake/FspsUpd.h | 128 ++++++++++++++++----- 3 files changed, 168 insertions(+), 66 deletions(-) (limited to 'src/vendorcode/intel') diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h index 0c910f3d93..58f4e39d78 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2020, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index b27514c644..cc44a2a96f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -259,7 +259,18 @@ typedef struct { /** Offset 0x014D - Reserved **/ - UINT8 Reserved3[14]; + UINT8 Reserved3[4]; + +/** Offset 0x0151 - PCH Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode +**/ + UINT8 PchTraceHubMode; + +/** Offset 0x0152 - Reserved +**/ + UINT8 Reserved4[9]; /** Offset 0x015B - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set @@ -269,7 +280,7 @@ typedef struct { /** Offset 0x015C - Reserved **/ - UINT8 Reserved4[4]; + UINT8 Reserved5[4]; /** Offset 0x0160 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine @@ -326,7 +337,7 @@ typedef struct { /** Offset 0x018B - Reserved **/ - UINT8 Reserved5; + UINT8 Reserved6; /** Offset 0x018C - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile @@ -337,7 +348,7 @@ typedef struct { /** Offset 0x018D - Reserved **/ - UINT8 Reserved6[3]; + UINT8 Reserved7[3]; /** Offset 0x0190 - SA GV System Agent dynamic frequency support and when enabled memory will be training @@ -348,7 +359,7 @@ typedef struct { /** Offset 0x0191 - Reserved **/ - UINT8 Reserved7[2]; + UINT8 Reserved8[2]; /** Offset 0x0193 - Rank Margin Tool Enable/disable Rank Margin Tool. @@ -390,7 +401,7 @@ typedef struct { /** Offset 0x019C - Reserved **/ - UINT8 Reserved8[2]; + UINT8 Reserved9[2]; /** Offset 0x019E - Memory Reference Clock 100MHz, 133MHz. @@ -400,7 +411,7 @@ typedef struct { /** Offset 0x019F - Reserved **/ - UINT8 Reserved9[22]; + UINT8 Reserved10[22]; /** Offset 0x01B5 - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller @@ -414,9 +425,16 @@ typedef struct { **/ UINT8 PchIshEnable; -/** Offset 0x01B7 - Reserved +/** Offset 0x01B7 - CPU Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode +**/ + UINT8 CpuTraceHubMode; + +/** Offset 0x01B8 - Reserved **/ - UINT8 Reserved10[166]; + UINT8 Reserved11[165]; /** Offset 0x025D - IMGU CLKOUT Configuration The configuration of IMGU CLKOUT, 0: Disable;1: Enable. @@ -426,7 +444,17 @@ typedef struct { /** Offset 0x0263 - Reserved **/ - UINT8 Reserved11[6]; + UINT8 Reserved12; + +/** Offset 0x0264 - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 CpuPcieRpEnableMask; + +/** Offset 0x0268 - Reserved +**/ + UINT8 Reserved13; /** Offset 0x0269 - RpClockReqMsgEnable **/ @@ -438,7 +466,7 @@ typedef struct { /** Offset 0x026E - Reserved **/ - UINT8 Reserved12[3]; + UINT8 Reserved14[3]; /** Offset 0x0271 - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -538,7 +566,7 @@ typedef struct { /** Offset 0x0281 - Reserved **/ - UINT8 Reserved13[126]; + UINT8 Reserved15[126]; /** Offset 0x02FF - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane @@ -547,7 +575,7 @@ typedef struct { /** Offset 0x0307 - Reserved **/ - UINT8 Reserved14[22]; + UINT8 Reserved16[22]; /** Offset 0x031D - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM @@ -559,7 +587,7 @@ typedef struct { /** Offset 0x031E - Reserved **/ - UINT8 Reserved15[5]; + UINT8 Reserved17[5]; /** Offset 0x0323 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; 1: Enable @@ -569,7 +597,7 @@ typedef struct { /** Offset 0x0324 - Reserved **/ - UINT8 Reserved16; + UINT8 Reserved18; /** Offset 0x0325 - CPU ratio value CPU ratio value. Valid Range 0 to 63 @@ -578,7 +606,7 @@ typedef struct { /** Offset 0x0326 - Reserved **/ - UINT8 Reserved17[2]; + UINT8 Reserved19[2]; /** Offset 0x0328 - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- @@ -589,7 +617,7 @@ typedef struct { /** Offset 0x0329 - Reserved **/ - UINT8 Reserved18; + UINT8 Reserved20; /** Offset 0x032A - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable. @@ -599,7 +627,7 @@ typedef struct { /** Offset 0x032B - Reserved **/ - UINT8 Reserved19[31]; + UINT8 Reserved21[31]; /** Offset 0x034A - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -613,7 +641,7 @@ typedef struct { /** Offset 0x034C - Reserved **/ - UINT8 Reserved20[4]; + UINT8 Reserved22[4]; /** Offset 0x0350 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -627,7 +655,7 @@ typedef struct { /** Offset 0x0358 - Reserved **/ - UINT8 Reserved21[8]; + UINT8 Reserved23[8]; /** Offset 0x0360 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable @@ -641,7 +669,7 @@ typedef struct { /** Offset 0x0368 - Reserved **/ - UINT8 Reserved22[522]; + UINT8 Reserved24[522]; /** Offset 0x0572 - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. @@ -650,7 +678,7 @@ typedef struct { /** Offset 0x0573 - Reserved **/ - UINT8 Reserved23[4]; + UINT8 Reserved25[4]; /** Offset 0x0577 - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use @@ -665,7 +693,7 @@ typedef struct { /** Offset 0x0597 - Reserved **/ - UINT8 Reserved24[5]; + UINT8 Reserved26[5]; /** Offset 0x059C - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -688,7 +716,7 @@ typedef struct { /** Offset 0x05A2 - Reserved **/ - UINT8 Reserved25[14]; + UINT8 Reserved27[14]; /** Offset 0x05B0 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -698,7 +726,7 @@ typedef struct { /** Offset 0x05B1 - Reserved **/ - UINT8 Reserved26[4]; + UINT8 Reserved28[4]; /** Offset 0x05B5 - MRC Safe Config Enables/Disable MRC Safe Config @@ -744,7 +772,7 @@ typedef struct { /** Offset 0x05BC - Reserved **/ - UINT8 Reserved27[4]; + UINT8 Reserved29[4]; /** Offset 0x05C0 - Early Command Training Enables/Disable Early Command Training @@ -754,7 +782,7 @@ typedef struct { /** Offset 0x05C1 - Reserved **/ - UINT8 Reserved28[109]; + UINT8 Reserved30[109]; /** Offset 0x062E - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -764,7 +792,7 @@ typedef struct { /** Offset 0x0630 - Reserved **/ - UINT8 Reserved29[62]; + UINT8 Reserved31[62]; /** Offset 0x066E - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, @@ -777,7 +805,7 @@ typedef struct { /** Offset 0x066F - Reserved **/ - UINT8 Reserved30[2]; + UINT8 Reserved32[2]; /** Offset 0x0671 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) @@ -787,7 +815,7 @@ typedef struct { /** Offset 0x0672 - Reserved **/ - UINT8 Reserved31[2]; + UINT8 Reserved33[2]; /** Offset 0x0674 - TCSS USB Port Enable Bitmap for per port enabling @@ -796,7 +824,7 @@ typedef struct { /** Offset 0x0675 - Reserved **/ - UINT8 Reserved32[80]; + UINT8 Reserved34[80]; /** Offset 0x06C5 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -807,7 +835,7 @@ typedef struct { /** Offset 0x06C6 - Reserved **/ - UINT8 Reserved33[2]; + UINT8 Reserved35[2]; /** Offset 0x06C8 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 @@ -817,7 +845,7 @@ typedef struct { /** Offset 0x06C9 - Reserved **/ - UINT8 Reserved34[122]; + UINT8 Reserved36[122]; /** Offset 0x0743 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. @@ -827,7 +855,7 @@ typedef struct { /** Offset 0x0744 - Reserved **/ - UINT8 Reserved35[3]; + UINT8 Reserved37[3]; /** Offset 0x0747 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -836,7 +864,7 @@ typedef struct { /** Offset 0x0749 - Reserved **/ - UINT8 Reserved36[3]; + UINT8 Reserved38[3]; /** Offset 0x074C - DMIC ClkA Pin Muxing (N - DMIC number) Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* @@ -856,7 +884,7 @@ typedef struct { /** Offset 0x075D - Reserved **/ - UINT8 Reserved37[3]; + UINT8 Reserved39[3]; /** Offset 0x0760 - DMIC Data Pin Muxing Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* @@ -893,7 +921,7 @@ typedef struct { /** Offset 0x0775 - Reserved **/ - UINT8 Reserved38[315]; + UINT8 Reserved40[315]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -914,7 +942,7 @@ typedef struct { /** Offset 0x08B0 **/ - UINT8 UnusedUpdSpace23[6]; + UINT8 UnusedUpdSpace22[6]; /** Offset 0x08B6 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 8ab5878f83..9b8db02fe0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -417,9 +417,15 @@ typedef struct { **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x048E - Reserved +/** Offset 0x048E - Enable D3 Hot in TCSS + This policy will enable/disable D3 hot support in IOM + $EN_DIS +**/ + UINT8 D3HotEnable; + +/** Offset 0x048F - Reserved **/ - UINT8 Reserved16[2]; + UINT8 Reserved16; /** Offset 0x0490 - TypeC port GPIO setting GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined @@ -430,7 +436,17 @@ typedef struct { /** Offset 0x04B0 - Reserved **/ - UINT8 Reserved17[30]; + UINT8 Reserved17[8]; + +/** Offset 0x04B8 - Enable D3 Cold in TCSS + This policy will enable/disable D3 cold support in IOM + $EN_DIS +**/ + UINT8 D3ColdEnable; + +/** Offset 0x04B9 - Reserved +**/ + UINT8 Reserved18[21]; /** Offset 0x04CE - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides @@ -444,7 +460,7 @@ typedef struct { /** Offset 0x04D2 - Reserved **/ - UINT8 Reserved18[2]; + UINT8 Reserved19[2]; /** Offset 0x04D4 - ITBT Root Port Enable ITBT Root Port Enable, 0:Disable, 1:Enable @@ -454,7 +470,7 @@ typedef struct { /** Offset 0x04D8 - Reserved **/ - UINT8 Reserved19[11]; + UINT8 Reserved20[11]; /** Offset 0x04E3 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -464,7 +480,7 @@ typedef struct { /** Offset 0x04E7 - Reserved **/ - UINT8 Reserved20[194]; + UINT8 Reserved21[194]; /** Offset 0x05A9 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit @@ -475,7 +491,16 @@ typedef struct { /** Offset 0x05AA - Reserved **/ - UINT8 Reserved21[60]; + UINT8 Reserved22[10]; + +/** Offset 0x05B4 - CpuMpPpi + Pointer for CpuMpPpi +**/ + UINT32 CpuMpPpi; + +/** Offset 0x05B8 - Reserved +**/ + UINT8 Reserved23[46]; /** Offset 0x05E6 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -485,7 +510,7 @@ typedef struct { /** Offset 0x05E7 - Reserved **/ - UINT8 Reserved22[36]; + UINT8 Reserved24[36]; /** Offset 0x060B - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -494,7 +519,7 @@ typedef struct { /** Offset 0x060C - Reserved **/ - UINT8 Reserved23[2]; + UINT8 Reserved25[2]; /** Offset 0x060E - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. @@ -518,7 +543,7 @@ typedef struct { /** Offset 0x061C - Reserved **/ - UINT8 Reserved24[2]; + UINT8 Reserved26[2]; /** Offset 0x061E - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region @@ -529,7 +554,18 @@ typedef struct { /** Offset 0x061F - Reserved **/ - UINT8 Reserved25[75]; + UINT8 Reserved27[2]; + +/** Offset 0x0621 - RTC Cmos Memory Lock + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcMemoryLock; + +/** Offset 0x0622 - Reserved +**/ + UINT8 Reserved28[72]; /** Offset 0x066A - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. @@ -543,16 +579,32 @@ typedef struct { /** Offset 0x069A - Reserved **/ - UINT8 Reserved26[168]; + UINT8 Reserved29[168]; /** Offset 0x0742 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[24]; -/** Offset 0x075A - Reserved +/** Offset 0x075A - Touch Host Controller Port 0 Assignment + Assign THC Port 0 + 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 **/ - UINT8 Reserved27[86]; + UINT8 ThcPort0Assignment; + +/** Offset 0x075B - Reserved +**/ + UINT8 Reserved30[5]; + +/** Offset 0x0760 - Touch Host Controller Port 1 Assignment + Assign THC Port 1 + 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 +**/ + UINT8 ThcPort1Assignment; + +/** Offset 0x0761 - Reserved +**/ + UINT8 Reserved31[79]; /** Offset 0x07B0 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is @@ -573,7 +625,7 @@ typedef struct { /** Offset 0x07F8 - Reserved **/ - UINT8 Reserved28[98]; + UINT8 Reserved32[98]; /** Offset 0x085A - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. @@ -583,7 +635,7 @@ typedef struct { /** Offset 0x085B - Reserved **/ - UINT8 Reserved29[50]; + UINT8 Reserved33[50]; /** Offset 0x088D - Enable SATA Port DmVal DITO multiplier. Default is 15. @@ -592,7 +644,7 @@ typedef struct { /** Offset 0x0895 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved34; /** Offset 0x0896 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -601,7 +653,7 @@ typedef struct { /** Offset 0x08A6 - Reserved **/ - UINT8 Reserved31[72]; + UINT8 Reserved35[72]; /** Offset 0x08EE - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. @@ -615,7 +667,7 @@ typedef struct { /** Offset 0x0908 - Reserved **/ - UINT8 Reserved32[16]; + UINT8 Reserved36[16]; /** Offset 0x0918 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time @@ -635,7 +687,7 @@ typedef struct { /** Offset 0x091A - Reserved **/ - UINT8 Reserved33[3]; + UINT8 Reserved37[3]; /** Offset 0x091D - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. @@ -646,7 +698,7 @@ typedef struct { /** Offset 0x091E - Reserved **/ - UINT8 Reserved34[434]; + UINT8 Reserved38[434]; /** Offset 0x0AD0 - RpPtmBytes **/ @@ -654,7 +706,7 @@ typedef struct { /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved35[101]; + UINT8 Reserved39[101]; /** Offset 0x0B39 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -672,7 +724,29 @@ typedef struct { /** Offset 0x0B3A - Reserved **/ - UINT8 Reserved36[264]; + UINT8 Reserved40[260]; + +/** Offset 0x0C3E - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x0C3F - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x0C40 - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x0C41 - Reserved +**/ + UINT8 Reserved41; /** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -686,7 +760,7 @@ typedef struct { /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved37[269]; + UINT8 Reserved42[269]; /** Offset 0x0DAF - LpmStateEnableMask **/ @@ -694,7 +768,7 @@ typedef struct { /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved38[80]; + UINT8 Reserved43[176]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -709,11 +783,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0E00 +/** Offset 0x0E60 **/ UINT8 UnusedUpdSpace34[6]; -/** Offset 0x0E06 +/** Offset 0x0E66 **/ UINT16 UpdTerminator; } FSPS_UPD; -- cgit v1.2.3