From 32c3069fd7d076a41ceb5a0453bd9ec1ec9f8559 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Mon, 26 Mar 2018 18:37:16 -0700 Subject: intel/fsp: Update cannonlake fsp header Fsp revison 7.x.2A.20 also updated MemInfoHob.h to fix SMBIOS Type 17 Offset 15h Speed report incorrectly issue. BUG=None TEST=Boot up with meowth platform and run dmidecode to see two dimm entries under Type 17. Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/25378 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/vendorcode/intel') diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h index 941a891bff..99dd815973 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h @@ -202,6 +202,7 @@ typedef struct { UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz. } DIMM_INFO; typedef struct { -- cgit v1.2.3