From 39a8040ddc551306d823d52a459fdb5dd717b2fe Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 4 Sep 2020 11:18:03 -0600 Subject: vc/amd/fsp/picasso: Sync FSP-S UPD header file Sync the UPD definitions with the latest auto-generated files. Definitions and usage will be updated in a subsequent FSP Integration Guide. Cq-Depend: chrome-internal:3247431 BUG=b:167421913, b:166519072, b:159664044 TEST=Boot morphius BRANCH=Zork Signed-off-by: Marshall Dawson Change-Id: Ic85e1f457c8932d933d8645738de68319dbf375a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45113 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Jason Glenesk Reviewed-by: Raul Rangel --- src/vendorcode/amd/fsp/picasso/FspsUpd.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/vendorcode') diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 5adbb81f6c..34c672d48d 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -31,7 +31,11 @@ typedef struct __packed { /** Offset 0x011D**/ uint8_t unused3; /** Offset 0x011E**/ uint32_t xhci_oc_pin_select; /** Offset 0x0122**/ uint8_t xhci0_force_gen1; - /** Offset 0x0123**/ uint8_t UnusedUpdSpace0[45]; + /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable; + /** Offset 0x0124**/ uint32_t gnb_ioapic_base; + /** Offset 0x0128**/ uint8_t gnb_ioapic_id; + /** Offset 0x0129**/ uint8_t fch_ioapic_id; + /** Offset 0x0126**/ uint8_t UnusedUpdSpace0[38]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; -- cgit v1.2.3