From 064a50160a55058a7baa00a91cbb9ceb0126cda6 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Fri, 8 Apr 2016 14:31:54 -0700 Subject: cpu/x86/tsc: Compile TSC timer for postcar as well Change-Id: I8fd79d438756aae03649e320d4d640cee284d88a Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/14298 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/cpu/x86/tsc/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index 7e2eab2062..9751cacc87 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -2,6 +2,7 @@ bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c endif -- cgit v1.2.3