From 0ccc3c49e47d46b6f2ad8d93182414850284ae70 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Tue, 10 Oct 2017 12:29:53 +0200 Subject: intel/fsp_broadwell_de: Add timestamp functionality Add a little code to enable timestamps on FSP based implementation of Broadwell-DE. I have tested it by reading back the timestamps with cbmem utility once the board has booted into Lubuntu. Change-Id: Idaa65a22a00382bf0c37acf2f5a1e07c6b1b42d9 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/21932 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/fsp_broadwell_de/Makefile.inc | 3 +++ .../fsp_broadwell_de/include/soc/broadwell_de.h | 3 +++ src/soc/intel/fsp_broadwell_de/tsc_freq.c | 28 ++++++++++++++++++++++ 3 files changed, 34 insertions(+) create mode 100644 src/soc/intel/fsp_broadwell_de/tsc_freq.c (limited to 'src') diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 028c45d6dc..38cc4411db 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -16,6 +16,7 @@ ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += northcluster.c ramstage-y += ramstage.c +ramstage-y += tsc_freq.c romstage-y += memmap.c ramstage-y += memmap.c ramstage-y += southcluster.c @@ -24,11 +25,13 @@ ramstage-y += reset.c ramstage-y += acpi.c ramstage-y += smbus_common.c ramstage-y += smbus.c +romstage-y += tsc_freq.c ramstage-y += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h index 4c11f386dd..dc1ec190a2 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h @@ -26,4 +26,7 @@ #define TSEG_BASE 0xa8 /* TSEG base */ #define TSEG_LIMIT 0xac /* TSEG limit */ +/* CPU bus clock is fixed at 100MHz */ +#define CPU_BCLK 100 + #endif /* _SOC_BROADWELL_DE_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/tsc_freq.c b/src/soc/intel/fsp_broadwell_de/tsc_freq.c new file mode 100644 index 0000000000..4225a3ab22 --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/tsc_freq.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return CPU_BCLK * ((platform_info.lo >> 8) & 0xff); +} -- cgit v1.2.3