From 14e22779625de673569c7b950ecc2753fb915b31 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 27 Apr 2010 06:56:47 +0000 Subject: Since some people disapprove of white space cleanups mixed in regular commits while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/Kconfig | 6 +- src/arch/i386/boot/acpi.c | 90 ++++----- src/arch/i386/boot/acpigen.c | 12 +- src/arch/i386/boot/boot.c | 12 +- src/arch/i386/boot/coreboot_table.c | 46 ++--- src/arch/i386/boot/mpspec.c | 10 +- src/arch/i386/boot/pirq_routing.c | 6 +- src/arch/i386/boot/tables.c | 10 +- src/arch/i386/boot/wakeup.S | 10 +- src/arch/i386/coreboot_ram.ld | 6 +- src/arch/i386/include/arch/acpi.h | 2 +- src/arch/i386/include/arch/coreboot_tables.h | 2 +- src/arch/i386/include/arch/cpu.h | 6 +- src/arch/i386/include/arch/io.h | 12 +- src/arch/i386/include/arch/pciconf.h | 2 +- src/arch/i386/include/arch/registers.h | 2 +- src/arch/i386/include/arch/romcc_io.h | 4 +- src/arch/i386/include/arch/smp/atomic.h | 16 +- src/arch/i386/include/arch/smp/mpspec.h | 14 +- src/arch/i386/include/bitops.h | 2 +- src/arch/i386/include/stdint.h | 8 +- src/arch/i386/init/bootblock_prologue.c | 2 +- src/arch/i386/init/crt0_prologue.inc | 2 +- src/arch/i386/init/crt0_romcc_epilogue.inc | 6 +- src/arch/i386/init/ldscript.ld | 2 +- src/arch/i386/lib/cbfs_and_run.c | 2 +- src/arch/i386/lib/cpu.c | 24 +-- src/arch/i386/lib/exception.c | 12 +- src/arch/i386/lib/id.inc | 4 +- src/arch/i386/lib/ioapic.c | 18 +- src/arch/i386/lib/pci_ops_auto.c | 6 +- src/arch/i386/lib/printk_init.c | 2 +- src/arch/i386/lib/stages.c | 2 +- src/arch/i386/llshell/console.inc | 6 +- src/arch/i386/llshell/llshell.inc | 26 +-- src/arch/i386/llshell/pci.inc | 14 +- src/arch/i386/llshell/ramtest.inc | 8 +- src/boot/hardwaremain.c | 12 +- src/console/Kconfig | 2 +- src/console/btext_console.c | 12 +- src/console/console.c | 8 +- src/console/logbuf_console.c | 2 +- src/console/uart8250_console.c | 6 +- src/console/vsprintf.c | 2 +- src/console/vtxprintf.c | 10 +- src/cpu/amd/dualcore/Makefile.inc | 2 +- src/cpu/amd/dualcore/amd_sibling.c | 20 +- src/cpu/amd/dualcore/dualcore_id.c | 8 +- src/cpu/amd/model_10xxx/Makefile.inc | 2 +- src/cpu/amd/model_10xxx/mc_patch_01000095.h | 2 +- src/cpu/amd/model_10xxx/model_10xxx_init.c | 12 +- src/cpu/amd/model_fxx/Makefile.inc | 2 +- src/cpu/amd/model_fxx/apic_timer.c | 2 +- src/cpu/amd/model_fxx/fidvid.c | 4 +- src/cpu/amd/model_fxx/microcode_rev_c.h | 2 +- src/cpu/amd/model_fxx/microcode_rev_d.h | 2 +- src/cpu/amd/model_fxx/microcode_rev_e.h | 2 +- src/cpu/amd/model_fxx/model_fxx_update_microcode.c | 6 +- src/cpu/amd/model_fxx/processor_name.c | 16 +- src/cpu/amd/model_gx2/cpubug.c | 42 ++-- src/cpu/amd/model_gx2/cpureginit.c | 28 +-- src/cpu/amd/model_lx/cpubug.c | 6 +- src/cpu/amd/model_lx/cpureginit.c | 4 +- src/cpu/amd/model_lx/msrinit.c | 6 +- src/cpu/amd/mtrr/amd_mtrr.c | 8 +- src/cpu/amd/sc520/raminit.c | 100 +++++----- src/cpu/amd/sc520/sc520.c | 20 +- src/cpu/intel/Makefile.inc | 2 +- src/cpu/intel/car/cache_as_ram.inc | 8 +- src/cpu/intel/hyperthreading/intel_sibling.c | 6 +- src/cpu/intel/microcode/microcode.c | 2 +- src/cpu/intel/model_1067x/model_1067x_init.c | 10 +- src/cpu/intel/model_106cx/cache_as_ram.inc | 16 +- src/cpu/intel/model_106cx/model_106cx_init.c | 8 +- src/cpu/intel/model_69x/model_69x_init.c | 2 +- src/cpu/intel/model_6bx/model_6bx_init.c | 8 +- src/cpu/intel/model_6dx/model_6dx_init.c | 2 +- src/cpu/intel/model_6ex/cache_as_ram.inc | 16 +- src/cpu/intel/model_6ex/model_6ex_init.c | 8 +- src/cpu/intel/model_6fx/cache_as_ram.inc | 16 +- src/cpu/intel/model_6fx/model_6fx_init.c | 10 +- src/cpu/intel/model_6xx/microcode_MU16810d.h | 6 +- src/cpu/intel/model_6xx/microcode_MU16830c.h | 6 +- src/cpu/intel/model_6xx/model_6xx_init.c | 4 +- src/cpu/intel/model_f0x/model_f0x_init.c | 4 +- src/cpu/intel/model_f0x/multiplier.h | 8 +- src/cpu/intel/model_f1x/model_f1x_init.c | 4 +- src/cpu/intel/model_f1x/multiplier.h | 8 +- src/cpu/intel/model_f2x/model_f2x_init.c | 2 +- src/cpu/intel/model_f3x/microcode_M1DF340E.h | 2 +- src/cpu/intel/model_f3x/microcode_M1DF3413.h | 8 +- src/cpu/intel/model_f3x/model_f3x_init.c | 4 +- src/cpu/intel/model_f4x/model_f4x_init.c | 4 +- src/cpu/intel/socket_mPGA604/Kconfig | 2 +- src/cpu/intel/speedstep/acpi.c | 2 +- src/cpu/via/car/cache_as_ram.inc | 18 +- src/cpu/via/model_c3/model_c3_init.c | 2 +- src/cpu/via/model_c7/model_c7_init.c | 6 +- src/cpu/x86/16bit/entry16.inc | 10 +- src/cpu/x86/16bit/reset16.lds | 2 +- src/cpu/x86/32bit/entry32.inc | 14 +- src/cpu/x86/lapic/lapic.c | 28 +-- src/cpu/x86/lapic/secondary.S | 2 +- src/cpu/x86/mtrr/earlymtrr.c | 4 +- src/cpu/x86/mtrr/mtrr.c | 32 ++-- src/cpu/x86/pae/pgtbl.c | 4 +- src/cpu/x86/smm/smiutil.c | 4 +- src/cpu/x86/smm/smm.ld | 4 +- src/cpu/x86/smm/smmhandler.S | 30 +-- src/cpu/x86/smm/smmrelocate.S | 12 +- src/cpu/x86/sse_disable.inc | 2 +- src/cpu/x86/tsc/delay_tsc.c | 10 +- src/devices/cardbus_device.c | 14 +- src/devices/device_util.c | 32 ++-- src/devices/hypertransport.c | 62 +++--- src/devices/oprom/include/x86emu/regs.h | 10 +- src/devices/oprom/include/x86emu/x86emu.h | 8 +- src/devices/oprom/x86.c | 22 +-- src/devices/oprom/x86_asm.S | 60 +++--- src/devices/oprom/x86_interrupts.c | 2 +- src/devices/oprom/x86emu/decode.c | 2 +- src/devices/oprom/x86emu/ops2.c | 2 +- src/devices/oprom/x86emu/sys.c | 6 +- src/devices/oprom/x86emu/x86emui.h | 2 +- src/devices/oprom/yabel/biosemu.c | 2 +- src/devices/oprom/yabel/biosemu.h | 2 +- src/devices/oprom/yabel/compat/functions.c | 2 +- src/devices/oprom/yabel/compat/of.h | 2 +- src/devices/oprom/yabel/compat/time.h | 2 +- src/devices/oprom/yabel/debug.h | 4 +- src/devices/oprom/yabel/interrupt.c | 14 +- src/devices/oprom/yabel/pmm.c | 12 +- src/devices/oprom/yabel/pmm.h | 2 +- src/devices/oprom/yabel/vbe.c | 6 +- src/devices/pci_device.c | 8 +- src/devices/pci_rom.c | 2 +- src/devices/pciexp_device.c | 4 +- src/devices/pcix_device.c | 12 +- src/devices/pnp_device.c | 14 +- src/devices/root_device.c | 10 +- src/drivers/ati/ragexl/atyfb.h | 2 +- src/drivers/ati/ragexl/fb.h | 14 +- src/drivers/ati/ragexl/fbcon.h | 6 +- src/drivers/ati/ragexl/mach64.h | 2 +- src/drivers/ati/ragexl/mach64_ct.c | 26 +-- src/drivers/ati/ragexl/xlinit.c | 98 +++++----- src/drivers/emulation/qemu/fb.h | 14 +- src/drivers/emulation/qemu/fbcon.h | 6 +- src/drivers/emulation/qemu/init.c | 2 +- src/drivers/generic/debug/debug_dev.c | 32 ++-- src/drivers/i2c/adm1026/adm1026.c | 6 +- src/drivers/i2c/adm1027/adm1027.c | 2 +- src/drivers/i2c/i2cmux/i2cmux.c | 4 +- src/drivers/i2c/i2cmux2/i2cmux2.c | 4 +- src/drivers/i2c/lm63/lm63.c | 6 +- src/drivers/si/3114/si_sata.c | 8 +- src/drivers/trident/blade3d/blade3d.c | 8 +- src/include/boot/coreboot_tables.h | 6 +- src/include/boot/elf_boot.h | 6 +- src/include/cbfs.h | 2 +- src/include/console/btext.h | 2 +- src/include/console/console.h | 2 +- src/include/console/vtxprintf.h | 2 +- src/include/cpu/amd/amdk8_sysconf.h | 2 +- src/include/cpu/amd/gx2def.h | 12 +- src/include/cpu/amd/lxdef.h | 8 +- src/include/cpu/amd/sc520.h | 16 +- src/include/cpu/amd/vr.h | 22 +-- src/include/cpu/x86/cache.h | 2 +- src/include/cpu/x86/msr.h | 2 +- src/include/cpu/x86/pae.h | 2 +- src/include/cpu/x86/smm.h | 6 +- src/include/cpu/x86/stack.h | 2 +- src/include/device/agp.h | 2 +- src/include/device/cardbus.h | 2 +- src/include/device/device.h | 10 +- src/include/device/hypertransport.h | 2 +- src/include/device/hypertransport_def.h | 2 +- src/include/device/pci.h | 2 +- src/include/device/pci_def.h | 10 +- src/include/device/pciexp.h | 2 +- src/include/device/pcix.h | 2 +- src/include/smp/atomic.h | 16 +- src/include/string.h | 14 +- src/lib/cbfs.c | 16 +- src/lib/cbmem.c | 10 +- src/lib/compute_ip_checksum.c | 2 +- src/lib/generic_dump_spd.c | 8 +- src/lib/generic_sdram.c | 2 +- src/lib/jpeg.c | 2 +- src/lib/lzma.c | 2 +- src/lib/lzmadecode.c | 40 ++-- src/lib/lzmadecode.h | 12 +- src/lib/nrv2b.c | 4 +- src/lib/ramtest.c | 6 +- src/lib/uart8250.c | 2 +- src/lib/usbdebug_direct.c | 22 +-- src/lib/xmodem.c | 2 +- src/mainboard/a-trend/Kconfig | 2 +- src/mainboard/abit/Kconfig | 2 +- src/mainboard/amd/rumba/devicetree.cb | 2 +- src/mainboard/amd/rumba/irq_tables.c | 2 +- src/mainboard/amd/rumba/mainboard.c | 2 +- src/mainboard/amd/rumba/romstage.c | 8 +- .../amd/serengeti_cheetah/acpi/amd8111.asl | 26 +-- .../amd/serengeti_cheetah/acpi/amd8111_isa.asl | 10 +- .../amd/serengeti_cheetah/acpi/amd8131.asl | 80 ++++---- .../amd/serengeti_cheetah/acpi/amd8131_2.asl | 30 +-- .../amd/serengeti_cheetah/acpi/amd8132_2.asl | 30 +-- .../amd/serengeti_cheetah/acpi/amd8151.asl | 14 +- src/mainboard/amd/serengeti_cheetah/ap_romstage.c | 2 +- src/mainboard/amd/serengeti_cheetah/devicetree.cb | 6 +- src/mainboard/amd/serengeti_cheetah/dsdt.asl | 10 +- src/mainboard/amd/serengeti_cheetah/fadt.c | 6 +- src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 16 +- src/mainboard/amd/serengeti_cheetah/irq_tables.c | 24 +-- src/mainboard/amd/serengeti_cheetah/mptable.c | 4 +- .../amd/serengeti_cheetah/readme_acpi.txt | 6 +- src/mainboard/amd/serengeti_cheetah/resourcemap.c | 6 +- src/mainboard/amd/serengeti_cheetah/romstage.c | 16 +- src/mainboard/amd/serengeti_cheetah/ssdt2.asl | 8 +- src/mainboard/amd/serengeti_cheetah/ssdt3.asl | 8 +- src/mainboard/amd/serengeti_cheetah/ssdt4.asl | 8 +- src/mainboard/arima/Kconfig | 2 +- src/mainboard/arima/hdama/debug.c | 18 +- src/mainboard/arima/hdama/devicetree.cb | 44 ++--- src/mainboard/arima/hdama/irq_tables.c | 2 +- src/mainboard/arima/hdama/mptable.c | 10 +- src/mainboard/artecgroup/Kconfig | 2 +- src/mainboard/artecgroup/dbe61/spd_table.h | 2 +- src/mainboard/asus/a8n_e/irq_tables.c | 2 +- src/mainboard/asus/a8v-e_se/acpi_tables.c | 4 +- src/mainboard/asus/a8v-e_se/romstage.c | 4 +- src/mainboard/asus/m2v-mx_se/acpi_tables.c | 4 +- src/mainboard/asus/m2v-mx_se/dsdt.asl | 6 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/mew-vm/devicetree.cb | 2 +- src/mainboard/asus/mew-vm/irq_tables.c | 4 +- src/mainboard/azza/Kconfig | 2 +- src/mainboard/biostar/Kconfig | 2 +- src/mainboard/broadcom/Kconfig | 2 +- src/mainboard/broadcom/blast/devicetree.cb | 6 +- src/mainboard/broadcom/blast/get_bus_conf.c | 8 +- src/mainboard/broadcom/blast/irq_tables.c | 18 +- src/mainboard/broadcom/blast/mptable.c | 18 +- src/mainboard/broadcom/blast/resourcemap.c | 14 +- src/mainboard/broadcom/blast/romstage.c | 12 +- src/mainboard/compaq/Kconfig | 2 +- src/mainboard/dell/s1850/debug.c | 58 +++--- src/mainboard/dell/s1850/devicetree.cb | 24 +-- src/mainboard/dell/s1850/irq_tables.c | 4 +- src/mainboard/dell/s1850/mptable.c | 8 +- src/mainboard/dell/s1850/romstage.c | 30 +-- src/mainboard/dell/s1850/s1850_fixups.c | 10 +- src/mainboard/dell/s1850/watchdog.c | 6 +- src/mainboard/digitallogic/Kconfig | 2 +- src/mainboard/digitallogic/adl855pc/devicetree.cb | 4 +- src/mainboard/digitallogic/adl855pc/irq_tables.c | 2 +- src/mainboard/digitallogic/adl855pc/romstage.c | 8 +- src/mainboard/digitallogic/msm586seg/devicetree.cb | 2 +- src/mainboard/digitallogic/msm586seg/irq_tables.c | 2 +- src/mainboard/digitallogic/msm586seg/mainboard.c | 22 +-- src/mainboard/digitallogic/msm586seg/romstage.c | 26 +-- src/mainboard/digitallogic/msm800sev/devicetree.cb | 4 +- src/mainboard/digitallogic/msm800sev/romstage.c | 2 +- src/mainboard/eaglelion/5bcm/devicetree.cb | 2 +- src/mainboard/eaglelion/5bcm/irq_tables.c | 2 +- src/mainboard/eaglelion/5bcm/romstage.c | 4 +- src/mainboard/emulation/qemu-x86/devicetree.cb | 2 +- src/mainboard/emulation/qemu-x86/irq_tables.c | 2 +- src/mainboard/emulation/qemu-x86/mainboard.c | 4 +- src/mainboard/emulation/qemu-x86/romstage.c | 4 +- src/mainboard/gigabyte/Kconfig | 2 +- src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 12 +- src/mainboard/gigabyte/m57sli/Kconfig | 14 +- src/mainboard/gigabyte/m57sli/Makefile.inc | 2 +- src/mainboard/gigabyte/m57sli/acpi_tables.c | 8 +- src/mainboard/gigabyte/m57sli/ap_romstage.c | 2 +- src/mainboard/gigabyte/m57sli/cmos.layout | 12 +- src/mainboard/gigabyte/m57sli/dsdt.asl | 6 +- src/mainboard/gigabyte/m57sli/get_bus_conf.c | 14 +- src/mainboard/gigabyte/m57sli/irq_tables.c | 18 +- src/mainboard/gigabyte/m57sli/mptable.c | 10 +- src/mainboard/gigabyte/m57sli/resourcemap.c | 12 +- src/mainboard/gigabyte/m57sli/romstage.c | 16 +- src/mainboard/hp/Kconfig | 2 +- src/mainboard/hp/dl145_g3/romstage.c | 2 +- src/mainboard/ibm/Kconfig | 2 +- src/mainboard/ibm/e325/devicetree.cb | 8 +- src/mainboard/ibm/e325/irq_tables.c | 2 +- src/mainboard/ibm/e325/resourcemap.c | 52 ++--- src/mainboard/ibm/e325/romstage.c | 4 +- src/mainboard/ibm/e326/devicetree.cb | 8 +- src/mainboard/ibm/e326/irq_tables.c | 2 +- src/mainboard/ibm/e326/resourcemap.c | 52 ++--- src/mainboard/ibm/e326/romstage.c | 4 +- src/mainboard/iei/nova4899r/irq_tables.c | 2 +- src/mainboard/iei/pcisa-lx-800-r10/Kconfig | 2 +- .../intel/d945gclf/acpi/i945_pci_irqs.asl | 2 +- .../intel/d945gclf/acpi/ich7_pci_irqs.asl | 2 +- src/mainboard/intel/d945gclf/acpi/mainboard.asl | 2 +- src/mainboard/intel/d945gclf/acpi/platform.asl | 8 +- src/mainboard/intel/d945gclf/acpi/thermal.asl | 2 +- src/mainboard/intel/d945gclf/acpi_tables.c | 2 +- src/mainboard/intel/d945gclf/chip.h | 2 +- src/mainboard/intel/d945gclf/cmos.layout | 2 +- src/mainboard/intel/d945gclf/devicetree.cb | 6 +- src/mainboard/intel/d945gclf/dsdt.asl | 2 +- src/mainboard/intel/d945gclf/mainboard_smi.c | 2 +- src/mainboard/intel/d945gclf/mptable.c | 2 +- src/mainboard/intel/d945gclf/romstage.c | 12 +- src/mainboard/intel/d945gclf/rtl8168.c | 2 +- src/mainboard/intel/eagleheights/Kconfig | 2 +- src/mainboard/intel/jarrell/debug.c | 64 +++---- src/mainboard/intel/jarrell/devicetree.cb | 8 +- src/mainboard/intel/jarrell/jarrell_fixups.c | 30 +-- src/mainboard/intel/jarrell/mptable.c | 6 +- src/mainboard/intel/jarrell/romstage.c | 12 +- src/mainboard/intel/jarrell/watchdog.c | 14 +- src/mainboard/intel/xe7501devkit/acpi_tables.c | 18 +- src/mainboard/intel/xe7501devkit/cmos.layout | 2 +- src/mainboard/intel/xe7501devkit/ioapic.h | 4 +- src/mainboard/intel/xe7501devkit/irq_tables.c | 10 +- src/mainboard/intel/xe7501devkit/mptable.c | 16 +- src/mainboard/intel/xe7501devkit/romstage.c | 6 +- src/mainboard/iwill/Kconfig | 2 +- src/mainboard/iwill/dk8_htx/acpi/amd8111.asl | 26 +-- src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl | 10 +- src/mainboard/iwill/dk8_htx/acpi/amd8131.asl | 80 ++++---- src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl | 30 +-- src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl | 30 +-- src/mainboard/iwill/dk8_htx/acpi/amd8151.asl | 14 +- src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl | 2 +- src/mainboard/iwill/dk8_htx/acpi_tables.c | 14 +- src/mainboard/iwill/dk8_htx/devicetree.cb | 4 +- src/mainboard/iwill/dk8_htx/dsdt.asl | 10 +- src/mainboard/iwill/dk8_htx/fadt.c | 6 +- src/mainboard/iwill/dk8_htx/get_bus_conf.c | 18 +- src/mainboard/iwill/dk8_htx/irq_tables.c | 24 +-- src/mainboard/iwill/dk8_htx/mptable.c | 8 +- src/mainboard/iwill/dk8_htx/resourcemap.c | 8 +- src/mainboard/iwill/dk8_htx/romstage.c | 14 +- src/mainboard/iwill/dk8_htx/ssdt2.asl | 8 +- src/mainboard/iwill/dk8_htx/ssdt3.asl | 8 +- src/mainboard/iwill/dk8_htx/ssdt4.asl | 8 +- src/mainboard/iwill/dk8_htx/ssdt5.asl | 8 +- src/mainboard/iwill/dk8s2/irq_tables.c | 2 +- src/mainboard/iwill/dk8s2/romstage.c | 12 +- src/mainboard/iwill/dk8x/devicetree.cb | 16 +- src/mainboard/iwill/dk8x/irq_tables.c | 6 +- src/mainboard/iwill/dk8x/romstage.c | 12 +- .../kontron/986lcd-m/acpi/i945_pci_irqs.asl | 2 +- .../kontron/986lcd-m/acpi/ich7_pci_irqs.asl | 2 +- src/mainboard/kontron/986lcd-m/acpi/platform.asl | 8 +- src/mainboard/kontron/986lcd-m/acpi/thermal.asl | 2 +- src/mainboard/kontron/986lcd-m/acpi_tables.c | 2 +- src/mainboard/kontron/986lcd-m/chip.h | 2 +- src/mainboard/kontron/986lcd-m/cmos.layout | 2 +- src/mainboard/kontron/986lcd-m/devicetree.cb | 4 +- src/mainboard/kontron/986lcd-m/dsdt.asl | 2 +- src/mainboard/kontron/986lcd-m/mainboard.c | 10 +- src/mainboard/kontron/986lcd-m/mainboard_smi.c | 2 +- src/mainboard/kontron/986lcd-m/mptable.c | 8 +- src/mainboard/kontron/986lcd-m/romstage.c | 20 +- src/mainboard/kontron/986lcd-m/rtl8168.c | 2 +- src/mainboard/kontron/kt690/acpi/routing.asl | 46 ++--- src/mainboard/lippert/Kconfig | 2 +- src/mainboard/lippert/frontrunner/devicetree.cb | 2 +- src/mainboard/lippert/frontrunner/irq_tables.c | 2 +- src/mainboard/lippert/frontrunner/romstage.c | 2 +- src/mainboard/mitac/Kconfig | 2 +- src/mainboard/msi/Kconfig | 2 +- src/mainboard/msi/ms6147/irq_tables.c | 2 +- src/mainboard/msi/ms7135/get_bus_conf.c | 4 +- src/mainboard/msi/ms7135/irq_tables.c | 12 +- src/mainboard/msi/ms7260/Kconfig | 12 +- src/mainboard/msi/ms7260/cmos.layout | 12 +- src/mainboard/msi/ms7260/resourcemap.c | 12 +- src/mainboard/msi/ms7260/romstage.c | 2 +- src/mainboard/msi/ms9282/Kconfig | 12 +- src/mainboard/msi/ms9282/Makefile.inc | 2 +- src/mainboard/msi/ms9652_fam10/acpi_tables.c | 8 +- src/mainboard/msi/ms9652_fam10/dsdt.asl | 6 +- src/mainboard/msi/ms9652_fam10/irq_tables.c | 18 +- src/mainboard/msi/ms9652_fam10/mb_sysconf.h | 2 +- src/mainboard/newisys/Kconfig | 2 +- src/mainboard/newisys/khepri/devicetree.cb | 8 +- src/mainboard/newisys/khepri/resourcemap.c | 6 +- src/mainboard/newisys/khepri/romstage.c | 10 +- src/mainboard/nvidia/Kconfig | 2 +- src/mainboard/nvidia/l1_2pvv/Kconfig | 12 +- src/mainboard/olpc/Kconfig | 2 +- src/mainboard/olpc/btest/devicetree.cb | 4 +- src/mainboard/olpc/btest/irq_tables.c | 2 +- src/mainboard/olpc/btest/mainboard.c | 42 ++-- src/mainboard/olpc/btest/romstage.c | 16 +- src/mainboard/olpc/rev_a/devicetree.cb | 4 +- src/mainboard/olpc/rev_a/irq_tables.c | 2 +- src/mainboard/olpc/rev_a/mainboard.c | 2 +- src/mainboard/olpc/rev_a/romstage.c | 16 +- src/mainboard/pcengines/Kconfig | 2 +- src/mainboard/pcengines/alix1c/Kconfig | 2 +- src/mainboard/pcengines/alix1c/devicetree.cb | 4 +- src/mainboard/rca/Kconfig | 2 +- src/mainboard/rca/rm4100/chip.h | 2 +- src/mainboard/rca/rm4100/gpio.c | 6 +- src/mainboard/rca/rm4100/mainboard.c | 2 +- src/mainboard/rca/rm4100/romstage.c | 4 +- src/mainboard/roda/rk886ex/acpi/battery.asl | 8 +- src/mainboard/roda/rk886ex/acpi/ec.asl | 4 +- src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl | 2 +- src/mainboard/roda/rk886ex/acpi/ich7_pci_irqs.asl | 2 +- src/mainboard/roda/rk886ex/acpi/mainboard.asl | 2 +- src/mainboard/roda/rk886ex/acpi/platform.asl | 8 +- src/mainboard/roda/rk886ex/acpi/superio.asl | 4 +- src/mainboard/roda/rk886ex/acpi/thermal.asl | 2 +- src/mainboard/roda/rk886ex/acpi_tables.c | 6 +- src/mainboard/roda/rk886ex/chip.h | 2 +- src/mainboard/roda/rk886ex/cmos.layout | 2 +- src/mainboard/roda/rk886ex/devicetree.cb | 6 +- src/mainboard/roda/rk886ex/dsdt.asl | 2 +- src/mainboard/roda/rk886ex/ec.c | 2 +- src/mainboard/roda/rk886ex/m3885.c | 14 +- src/mainboard/roda/rk886ex/mainboard.c | 2 +- src/mainboard/roda/rk886ex/mainboard_smi.c | 2 +- src/mainboard/roda/rk886ex/mptable.c | 2 +- src/mainboard/roda/rk886ex/romstage.c | 14 +- src/mainboard/roda/rk886ex/rtl8168.c | 2 +- src/mainboard/soyo/Kconfig | 2 +- src/mainboard/sunw/Kconfig | 2 +- src/mainboard/sunw/ultra40/devicetree.cb | 52 ++--- src/mainboard/sunw/ultra40/get_bus_conf.c | 14 +- src/mainboard/sunw/ultra40/irq_tables.c | 28 +-- src/mainboard/sunw/ultra40/mptable.c | 4 +- src/mainboard/sunw/ultra40/resourcemap.c | 8 +- src/mainboard/sunw/ultra40/romstage.c | 22 +-- src/mainboard/supermicro/Kconfig | 2 +- src/mainboard/supermicro/h8dme/ap_romstage.c | 2 +- src/mainboard/supermicro/h8dme/cmos.layout | 12 +- src/mainboard/supermicro/h8dme/devicetree.cb | 32 ++-- src/mainboard/supermicro/h8dme/get_bus_conf.c | 12 +- src/mainboard/supermicro/h8dme/irq_tables.c | 18 +- src/mainboard/supermicro/h8dme/mptable.c | 6 +- src/mainboard/supermicro/h8dme/resourcemap.c | 10 +- src/mainboard/supermicro/h8dmr/ap_romstage.c | 2 +- src/mainboard/supermicro/h8dmr/cmos.layout | 12 +- src/mainboard/supermicro/h8dmr/devicetree.cb | 52 ++--- src/mainboard/supermicro/h8dmr/get_bus_conf.c | 12 +- src/mainboard/supermicro/h8dmr/irq_tables.c | 18 +- src/mainboard/supermicro/h8dmr/mptable.c | 6 +- src/mainboard/supermicro/h8dmr/resourcemap.c | 10 +- src/mainboard/supermicro/h8dmr/romstage.c | 12 +- src/mainboard/supermicro/h8dmr_fam10/cmos.layout | 12 +- src/mainboard/supermicro/h8dmr_fam10/devicetree.cb | 50 ++--- src/mainboard/supermicro/h8dmr_fam10/irq_tables.c | 18 +- src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h | 2 +- src/mainboard/supermicro/h8dmr_fam10/resourcemap.c | 10 +- src/mainboard/supermicro/h8qme_fam10/cmos.layout | 12 +- src/mainboard/supermicro/h8qme_fam10/devicetree.cb | 26 +-- src/mainboard/supermicro/h8qme_fam10/irq_tables.c | 18 +- src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h | 2 +- src/mainboard/supermicro/h8qme_fam10/mptable.c | 26 +-- src/mainboard/supermicro/h8qme_fam10/resourcemap.c | 10 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 12 +- src/mainboard/supermicro/x6dai_g/debug.c | 64 +++---- src/mainboard/supermicro/x6dai_g/devicetree.cb | 14 +- src/mainboard/supermicro/x6dai_g/mptable.c | 4 +- src/mainboard/supermicro/x6dai_g/romstage.c | 10 +- src/mainboard/supermicro/x6dai_g/watchdog.c | 6 +- src/mainboard/supermicro/x6dhe_g/debug.c | 64 +++---- src/mainboard/supermicro/x6dhe_g/devicetree.cb | 22 +-- src/mainboard/supermicro/x6dhe_g/mptable.c | 6 +- src/mainboard/supermicro/x6dhe_g/romstage.c | 12 +- src/mainboard/supermicro/x6dhe_g/watchdog.c | 8 +- src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c | 4 +- src/mainboard/supermicro/x6dhe_g2/debug.c | 64 +++---- src/mainboard/supermicro/x6dhe_g2/devicetree.cb | 24 +-- src/mainboard/supermicro/x6dhe_g2/mptable.c | 6 +- src/mainboard/supermicro/x6dhe_g2/romstage.c | 12 +- src/mainboard/supermicro/x6dhe_g2/watchdog.c | 8 +- .../supermicro/x6dhe_g2/x6dhe_g2_fixups.c | 4 +- src/mainboard/supermicro/x6dhr_ig/debug.c | 64 +++---- src/mainboard/supermicro/x6dhr_ig/devicetree.cb | 26 +-- src/mainboard/supermicro/x6dhr_ig/mptable.c | 8 +- src/mainboard/supermicro/x6dhr_ig/romstage.c | 12 +- src/mainboard/supermicro/x6dhr_ig/watchdog.c | 8 +- src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c | 4 +- src/mainboard/supermicro/x6dhr_ig2/debug.c | 64 +++---- src/mainboard/supermicro/x6dhr_ig2/devicetree.cb | 24 +-- src/mainboard/supermicro/x6dhr_ig2/mptable.c | 8 +- src/mainboard/supermicro/x6dhr_ig2/romstage.c | 12 +- src/mainboard/supermicro/x6dhr_ig2/watchdog.c | 8 +- src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c | 4 +- src/mainboard/technexion/Kconfig | 2 +- src/mainboard/technexion/tim5690/mainboard.c | 2 +- src/mainboard/technexion/tim5690/speaker.c | 2 +- src/mainboard/technexion/tim8690/mainboard.c | 2 +- src/mainboard/technologic/Kconfig | 2 +- src/mainboard/technologic/ts5300/chip.h | 2 +- src/mainboard/technologic/ts5300/devicetree.cb | 4 +- src/mainboard/technologic/ts5300/irq_tables.c | 2 +- src/mainboard/technologic/ts5300/mainboard.c | 14 +- src/mainboard/technologic/ts5300/romstage.c | 46 ++--- src/mainboard/thomson/Kconfig | 2 +- src/mainboard/thomson/ip1000/gpio.c | 6 +- src/mainboard/thomson/ip1000/mainboard.c | 10 +- src/mainboard/thomson/ip1000/romstage.c | 2 +- src/mainboard/tyan/Kconfig | 2 +- src/mainboard/tyan/s2735/Kconfig | 4 +- src/mainboard/tyan/s2735/cmos.layout | 4 +- src/mainboard/tyan/s2735/devicetree.cb | 6 +- src/mainboard/tyan/s2735/irq_tables.c | 2 +- src/mainboard/tyan/s2735/mptable.c | 8 +- src/mainboard/tyan/s2735/romstage.c | 4 +- src/mainboard/tyan/s2850/devicetree.cb | 20 +- src/mainboard/tyan/s2850/irq_tables.c | 2 +- src/mainboard/tyan/s2850/mptable.c | 14 +- src/mainboard/tyan/s2850/romstage.c | 6 +- src/mainboard/tyan/s2875/devicetree.cb | 12 +- src/mainboard/tyan/s2875/irq_tables.c | 2 +- src/mainboard/tyan/s2875/mptable.c | 16 +- src/mainboard/tyan/s2875/romstage.c | 4 +- src/mainboard/tyan/s2880/devicetree.cb | 12 +- src/mainboard/tyan/s2880/irq_tables.c | 4 +- src/mainboard/tyan/s2880/mptable.c | 22 +-- src/mainboard/tyan/s2880/romstage.c | 6 +- src/mainboard/tyan/s2881/devicetree.cb | 16 +- src/mainboard/tyan/s2881/get_bus_conf.c | 10 +- src/mainboard/tyan/s2881/irq_tables.c | 20 +- src/mainboard/tyan/s2881/mainboard.c | 2 +- src/mainboard/tyan/s2881/mptable.c | 10 +- src/mainboard/tyan/s2881/resourcemap.c | 6 +- src/mainboard/tyan/s2881/romstage.c | 4 +- src/mainboard/tyan/s2882/devicetree.cb | 14 +- src/mainboard/tyan/s2882/irq_tables.c | 26 +-- src/mainboard/tyan/s2882/mptable.c | 18 +- src/mainboard/tyan/s2882/romstage.c | 6 +- src/mainboard/tyan/s2885/devicetree.cb | 28 +-- src/mainboard/tyan/s2885/get_bus_conf.c | 10 +- src/mainboard/tyan/s2885/irq_tables.c | 22 +-- src/mainboard/tyan/s2885/mptable.c | 8 +- src/mainboard/tyan/s2885/resourcemap.c | 6 +- src/mainboard/tyan/s2885/romstage.c | 8 +- src/mainboard/tyan/s2891/resourcemap.c | 12 +- src/mainboard/tyan/s2892/dsdt.asl | 10 +- src/mainboard/tyan/s2895/dsdt.asl | 10 +- src/mainboard/tyan/s2912/Kconfig | 12 +- src/mainboard/tyan/s2912/ap_romstage.c | 2 +- src/mainboard/tyan/s2912/get_bus_conf.c | 4 +- src/mainboard/tyan/s2912/mb_sysconf.h | 2 +- src/mainboard/tyan/s2912_fam10/irq_tables.c | 18 +- src/mainboard/tyan/s2912_fam10/mb_sysconf.h | 2 +- src/mainboard/tyan/s4880/devicetree.cb | 8 +- src/mainboard/tyan/s4880/irq_tables.c | 2 +- src/mainboard/tyan/s4880/mptable.c | 26 +-- src/mainboard/tyan/s4880/resourcemap.c | 6 +- src/mainboard/tyan/s4880/romstage.c | 8 +- src/mainboard/tyan/s4882/devicetree.cb | 20 +- src/mainboard/tyan/s4882/irq_tables.c | 2 +- src/mainboard/tyan/s4882/mptable.c | 28 +-- src/mainboard/tyan/s4882/resourcemap.c | 6 +- src/mainboard/tyan/s4882/romstage.c | 10 +- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m/acpi_tables.c | 10 +- src/mainboard/via/epia-m/devicetree.cb | 6 +- src/mainboard/via/epia-m/dsdt.asl | 56 +++--- src/mainboard/via/epia-m/dsdt.c | 6 +- src/mainboard/via/epia-m/irq_tables.c | 2 +- src/mainboard/via/epia-m/romstage.c | 16 +- src/mainboard/via/epia-m700/romstage.c | 4 +- src/mainboard/via/epia-n/acpi_tables.c | 10 +- src/mainboard/via/epia-n/dsdt.asl | 2 +- src/mainboard/via/epia-n/romstage.c | 16 +- src/mainboard/via/epia/irq_tables.c | 2 +- src/mainboard/via/epia/romstage.c | 16 +- src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl | 108 +++++------ src/mainboard/via/vt8454c/acpi/irq.asl | 212 ++++++++++----------- src/mainboard/via/vt8454c/acpi_tables.c | 2 +- src/mainboard/via/vt8454c/dsdt.asl | 54 +++--- src/mainboard/via/vt8454c/romstage.c | 4 +- src/mainboard/winent/pl6064/devicetree.cb | 2 +- src/northbridge/amd/amdfam10/amdfam10_conf.c | 2 +- src/northbridge/amd/amdk8/amdk8_f.h | 32 ++-- src/northbridge/amd/amdk8/exit_from_self.c | 2 +- src/northbridge/amd/amdk8/misc_control.c | 20 +- src/northbridge/amd/amdk8/raminit.c | 2 +- src/northbridge/amd/amdk8/raminit_f.c | 18 +- src/northbridge/amd/amdk8/raminit_f_dqs.c | 14 +- src/northbridge/amd/amdk8/setup_resource_map.c | 2 +- src/northbridge/amd/amdmct/mct/mct_d.c | 2 +- src/northbridge/amd/gx1/northbridge.c | 12 +- src/northbridge/amd/gx1/raminit.c | 24 +-- src/northbridge/amd/gx2/chipsetinit.c | 30 +-- src/northbridge/amd/gx2/grphinit.c | 2 +- src/northbridge/amd/gx2/northbridge.c | 26 +-- src/northbridge/amd/gx2/northbridgeinit.c | 84 ++++---- src/northbridge/amd/gx2/pll_reset.c | 26 +-- src/northbridge/amd/gx2/raminit.c | 8 +- src/northbridge/amd/lx/Kconfig | 2 +- src/northbridge/amd/lx/grphinit.c | 8 +- src/northbridge/amd/lx/northbridge.c | 2 +- src/northbridge/amd/lx/raminit.c | 14 +- src/northbridge/intel/e7501/debug.c | 28 +-- src/northbridge/intel/e7501/northbridge.c | 6 +- src/northbridge/intel/e7501/raminit.c | 102 +++++----- src/northbridge/intel/e7501/raminit.h | 4 +- src/northbridge/intel/e7501/reset_test.c | 8 +- src/northbridge/intel/e7520/memory_initialized.c | 2 +- src/northbridge/intel/e7520/northbridge.c | 4 +- src/northbridge/intel/e7520/pciexp_porta.c | 8 +- src/northbridge/intel/e7520/pciexp_porta1.c | 8 +- src/northbridge/intel/e7520/pciexp_portb.c | 8 +- src/northbridge/intel/e7520/pciexp_portc.c | 8 +- src/northbridge/intel/e7520/raminit.c | 194 +++++++++---------- src/northbridge/intel/e7525/memory_initialized.c | 2 +- src/northbridge/intel/e7525/northbridge.c | 4 +- src/northbridge/intel/e7525/pciexp_porta.c | 8 +- src/northbridge/intel/e7525/pciexp_porta1.c | 8 +- src/northbridge/intel/e7525/pciexp_portb.c | 8 +- src/northbridge/intel/e7525/pciexp_portc.c | 8 +- src/northbridge/intel/e7525/raminit.c | 192 +++++++++---------- src/northbridge/intel/i3100/pciexp_porta_ep80579.c | 2 +- src/northbridge/intel/i3100/raminit_ep80579.c | 56 +++--- src/northbridge/intel/i440bx/Kconfig | 2 +- src/northbridge/intel/i440bx/debug.c | 4 +- src/northbridge/intel/i440bx/i440bx.h | 4 +- src/northbridge/intel/i440lx/Makefile.inc | 2 +- src/northbridge/intel/i440lx/northbridge.c | 2 +- src/northbridge/intel/i440lx/raminit.c | 48 ++--- src/northbridge/intel/i82810/debug.c | 4 +- src/northbridge/intel/i82810/raminit.c | 6 +- src/northbridge/intel/i82810/raminit.h | 4 +- src/northbridge/intel/i82830/i82830_smihandler.c | 12 +- src/northbridge/intel/i82830/vga.c | 2 +- src/northbridge/intel/i855/debug.c | 18 +- src/northbridge/intel/i855/northbridge.c | 10 +- src/northbridge/intel/i855/raminit.c | 56 +++--- src/northbridge/intel/i855/reset_test.c | 8 +- src/northbridge/intel/i945/debug.c | 14 +- src/northbridge/intel/i945/raminit.c | 2 +- src/northbridge/via/cn400/northbridge.c | 6 +- src/northbridge/via/cn400/raminit.c | 180 ++++++++--------- src/northbridge/via/cn400/vga.c | 4 +- src/northbridge/via/cn700/raminit.c | 6 +- src/northbridge/via/cn700/vga.c | 4 +- src/northbridge/via/cx700/cx700_early_serial.c | 2 +- src/northbridge/via/cx700/cx700_vga.c | 4 +- src/northbridge/via/cx700/raminit.c | 4 +- src/northbridge/via/vt8601/northbridge.c | 12 +- src/northbridge/via/vt8601/raminit.c | 20 +- src/northbridge/via/vt8623/northbridge.c | 12 +- src/northbridge/via/vt8623/raminit.c | 34 ++-- src/northbridge/via/vt8623/vga.c | 8 +- src/northbridge/via/vx800/dev_init.c | 74 +++---- src/northbridge/via/vx800/dqs_search.c | 14 +- src/northbridge/via/vx800/dram_util.c | 30 +-- src/northbridge/via/vx800/driving_setting.c | 4 +- .../via/vx800/examples/driving_clk_phase_data.c | 4 +- src/northbridge/via/vx800/examples/romstage.c | 46 ++--- src/northbridge/via/vx800/final_setting.c | 4 +- src/northbridge/via/vx800/freq_setting.c | 2 +- src/northbridge/via/vx800/northbridge.c | 2 +- src/northbridge/via/vx800/rank_map.c | 30 +-- src/northbridge/via/vx800/timing_setting.c | 2 +- src/northbridge/via/vx800/uma_ram_setting.c | 6 +- src/northbridge/via/vx800/vga.c | 28 +-- src/northbridge/via/vx800/vx800_early_serial.c | 2 +- src/northbridge/via/vx800/vx800_early_smbus.c | 8 +- src/northbridge/via/vx800/vx800_lpc.c | 18 +- src/pc80/Makefile.inc | 2 +- src/pc80/i8259.c | 6 +- src/pc80/mc146818rtc.c | 10 +- src/pc80/mc146818rtc_early.c | 2 +- src/pc80/serial.c | 6 +- src/southbridge/amd/amd8111/amd8111.c | 8 +- src/southbridge/amd/amd8111/amd8111_ac97.c | 2 +- src/southbridge/amd/amd8111/amd8111_acpi.c | 16 +- src/southbridge/amd/amd8111/amd8111_ide.c | 2 +- src/southbridge/amd/amd8111/amd8111_lpc.c | 12 +- src/southbridge/amd/amd8111/amd8111_nic.c | 22 +-- src/southbridge/amd/amd8111/amd8111_reset.c | 2 +- src/southbridge/amd/amd8111/amd8111_smbus.c | 2 +- src/southbridge/amd/amd8111/amd8111_smbus.h | 10 +- src/southbridge/amd/amd8111/amd8111_usb.c | 2 +- src/southbridge/amd/amd8111/amd8111_usb2.c | 4 +- src/southbridge/amd/amd8111/chip.h | 2 +- .../amd/amd8131-disable/amd8131_bridge.c | 2 +- src/southbridge/amd/amd8131/amd8131_bridge.c | 26 +-- src/southbridge/amd/amd8132/amd8132_bridge.c | 16 +- src/southbridge/amd/amd8151/amd8151_agp3.c | 4 +- src/southbridge/amd/cs5535/cs5535.c | 4 +- src/southbridge/amd/cs5535/cs5535_early_setup.c | 4 +- src/southbridge/amd/cs5535/cs5535_early_smbus.c | 2 +- src/southbridge/amd/cs5535/cs5535_smbus.h | 6 +- src/southbridge/amd/cs5536/Kconfig | 2 +- src/southbridge/amd/cs5536/cs5536.c | 24 +-- src/southbridge/amd/cs5536/cs5536.h | 2 +- src/southbridge/amd/cs5536/cs5536_smbus2.h | 2 +- src/southbridge/broadcom/bcm5780/bcm5780_pcix.c | 4 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 4 +- .../broadcom/bcm5785/bcm5785_early_setup.c | 2 +- .../broadcom/bcm5785/bcm5785_early_smbus.c | 4 +- src/southbridge/broadcom/bcm5785/bcm5785_lpc.c | 22 +-- src/southbridge/broadcom/bcm5785/bcm5785_sata.c | 2 +- .../broadcom/bcm5785/bcm5785_sb_pci_main.c | 14 +- src/southbridge/broadcom/bcm5785/bcm5785_smbus.h | 10 +- src/southbridge/broadcom/bcm5785/bcm5785_usb.c | 4 +- src/southbridge/broadcom/bcm5785/chip.h | 2 +- src/southbridge/intel/esb6300/chip.h | 2 +- src/southbridge/intel/esb6300/esb6300.c | 4 +- src/southbridge/intel/esb6300/esb6300_ac97.c | 2 +- .../intel/esb6300/esb6300_early_smbus.c | 26 +-- src/southbridge/intel/esb6300/esb6300_ehci.c | 4 +- src/southbridge/intel/esb6300/esb6300_ide.c | 4 +- src/southbridge/intel/esb6300/esb6300_lpc.c | 14 +- src/southbridge/intel/esb6300/esb6300_pic.c | 2 +- src/southbridge/intel/esb6300/esb6300_sata.c | 18 +- src/southbridge/intel/esb6300/esb6300_smbus.h | 2 +- src/southbridge/intel/esb6300/esb6300_uhci.c | 2 +- src/southbridge/intel/i3100/i3100_lpc.c | 12 +- src/southbridge/intel/i3100/i3100_sata.c | 14 +- src/southbridge/intel/i82371eb/i82371eb_smbus.h | 14 +- src/southbridge/intel/i82801ax/i82801ax_ide.c | 2 +- src/southbridge/intel/i82801ax/i82801ax_lpc.c | 4 +- src/southbridge/intel/i82801bx/i82801bx_ide.c | 2 +- src/southbridge/intel/i82801bx/i82801bx_lpc.c | 4 +- src/southbridge/intel/i82801bx/i82801bx_smbus.h | 2 +- src/southbridge/intel/i82801cx/chip.h | 2 +- src/southbridge/intel/i82801cx/i82801cx.c | 2 +- src/southbridge/intel/i82801cx/i82801cx.h | 4 +- .../intel/i82801cx/i82801cx_early_smbus.c | 10 +- src/southbridge/intel/i82801cx/i82801cx_lpc.c | 38 ++-- src/southbridge/intel/i82801cx/i82801cx_smbus.c | 6 +- src/southbridge/intel/i82801cx/i82801cx_usb.c | 4 +- src/southbridge/intel/i82801dx/i82801dx.c | 2 +- src/southbridge/intel/i82801dx/i82801dx.h | 12 +- .../intel/i82801dx/i82801dx_early_smbus.c | 2 +- src/southbridge/intel/i82801ex/chip.h | 2 +- src/southbridge/intel/i82801ex/i82801ex.c | 4 +- src/southbridge/intel/i82801ex/i82801ex_ac97.c | 2 +- .../intel/i82801ex/i82801ex_early_smbus.c | 28 +-- src/southbridge/intel/i82801ex/i82801ex_ehci.c | 4 +- src/southbridge/intel/i82801ex/i82801ex_ide.c | 2 +- src/southbridge/intel/i82801ex/i82801ex_lpc.c | 14 +- src/southbridge/intel/i82801ex/i82801ex_pci.c | 4 +- src/southbridge/intel/i82801ex/i82801ex_sata.c | 6 +- src/southbridge/intel/i82801ex/i82801ex_smbus.h | 2 +- src/southbridge/intel/i82801ex/i82801ex_uhci.c | 2 +- src/southbridge/intel/i82801gx/i82801gx_azalia.c | 2 +- src/southbridge/intel/i82870/p64h2_ioapic.c | 10 +- src/southbridge/intel/i82870/p64h2_pcibridge.c | 4 +- src/southbridge/intel/pxhd/pxhd_bridge.c | 24 +-- src/southbridge/nvidia/mcp55/mcp55_fadt.c | 6 +- src/southbridge/nvidia/mcp55/mcp55_lpc.c | 2 +- src/southbridge/ricoh/rl5c476/rl5c476.c | 10 +- src/southbridge/ricoh/rl5c476/rl5c476.h | 2 +- src/southbridge/sis/sis966/sis966_lpc.c | 2 +- src/southbridge/via/k8t890/k8t890_bridge.c | 6 +- src/southbridge/via/k8t890/k8t890_ctrl.c | 2 +- src/southbridge/via/k8t890/k8t890_early_car.c | 4 +- src/southbridge/via/k8t890/k8t890_host_ctrl.c | 2 +- src/southbridge/via/k8t890/romstrap.inc | 2 +- src/southbridge/via/vt8231/vt8231.c | 6 +- src/southbridge/via/vt8231/vt8231_acpi.c | 12 +- src/southbridge/via/vt8231/vt8231_early_serial.c | 16 +- src/southbridge/via/vt8231/vt8231_early_smbus.c | 4 +- src/southbridge/via/vt8231/vt8231_ide.c | 38 ++-- src/southbridge/via/vt8231/vt8231_lpc.c | 32 ++-- src/southbridge/via/vt8231/vt8231_nic.c | 2 +- src/southbridge/via/vt8231/vt8231_usb.c | 20 +- src/southbridge/via/vt8235/vt8235.c | 12 +- src/southbridge/via/vt8235/vt8235_early_serial.c | 12 +- src/southbridge/via/vt8235/vt8235_early_smbus.c | 74 +++---- src/southbridge/via/vt8235/vt8235_ide.c | 38 ++-- src/southbridge/via/vt8235/vt8235_lpc.c | 36 ++-- src/southbridge/via/vt8235/vt8235_nic.c | 2 +- src/southbridge/via/vt8237r/vt8237r_early_smbus.c | 8 +- src/southbridge/via/vt8237r/vt8237r_lpc.c | 16 +- src/superio/Makefile.inc | 2 +- .../smsc/lpc47n227/lpc47n227_early_serial.c | 6 +- src/superio/smsc/lpc47n227/superio.c | 16 +- src/superio/winbond/w83627hf/superio.c | 2 +- 782 files changed, 4575 insertions(+), 4575 deletions(-) (limited to 'src') diff --git a/src/Kconfig b/src/Kconfig index 026e99da78..67ac5753a7 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -454,8 +454,8 @@ config FALLBACK_BOOTSPLASH_FILE depends on BOOTSPLASH default "bootsplash.jpg" help - The path and filename of the file to use as graphical bootsplash - screen. The file format has to be jpg. + The path and filename of the file to use as graphical bootsplash + screen. The file format has to be jpg. # TODO: Turn this into a "choice". config FRAMEBUFFER_VESA_MODE @@ -568,7 +568,7 @@ config X86EMU_DEBUG_TRACE depends on X86EMU_DEBUG help Print _all_ opcodes that are executed by x86emu. - + WARNING: This will produce a LOT of output and take a long time. Note: This option will increase the size of the coreboot image. diff --git a/src/arch/i386/boot/acpi.c b/src/arch/i386/boot/acpi.c index 9bab92831f..e5169eaf43 100644 --- a/src/arch/i386/boot/acpi.c +++ b/src/arch/i386/boot/acpi.c @@ -7,7 +7,7 @@ * Copyright (C) 2004 SUSE LINUX AG * Copyright (C) 2005-2009 coresystems GmbH * - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * Nick Barker , and those portions * Copyright (C) 2004 Nick Barker * @@ -15,12 +15,12 @@ * 2005.9 yhlu add SRAT table generation */ -/* +/* * Each system port implementing ACPI has to provide two functions: - * + * * write_acpi_tables() * acpi_dump_apics() - * + * * See Kontron 986LCD-M port for a good example of an ACPI implementation * in coreboot. */ @@ -59,10 +59,10 @@ void acpi_add_table(acpi_rsdp_t *rsdp, void *table) if (rsdp->xsdt_address) { xsdt = (acpi_xsdt_t *)((u32)rsdp->xsdt_address); } - + /* This should always be MAX_ACPI_TABLES */ entries_num = ARRAY_SIZE(rsdt->entry); - + for (i = 0; i < entries_num; i++) { if(rsdt->entry[i] == 0) break; @@ -120,10 +120,10 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) lapic->type=0; lapic->length=sizeof(acpi_madt_lapic_t); lapic->flags=1; - + lapic->processor_id=cpu; lapic->apic_id=apic; - + return(lapic->length); } @@ -146,16 +146,16 @@ unsigned long acpi_create_madt_lapics(unsigned long current) return current; } -int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,u32 gsi_base) +int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,u32 gsi_base) { ioapic->type=1; ioapic->length=sizeof(acpi_madt_ioapic_t); ioapic->reserved=0x00; ioapic->gsi_base=gsi_base; - + ioapic->ioapic_id=id; ioapic->ioapic_addr=addr; - + return(ioapic->length); } @@ -168,7 +168,7 @@ int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, irqoverride->source=source; irqoverride->gsirq=gsirq; irqoverride->flags=flags; - + return(irqoverride->length); } @@ -177,29 +177,29 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, { lapic_nmi->type=4; lapic_nmi->length=sizeof(acpi_madt_lapic_nmi_t); - + lapic_nmi->flags=flags; lapic_nmi->processor_id=cpu; lapic_nmi->lint=lint; - + return(lapic_nmi->length); } void acpi_create_madt(acpi_madt_t *madt) { #define LOCAL_APIC_ADDR 0xfee00000ULL - + acpi_header_t *header=&(madt->header); unsigned long current=(unsigned long)madt+sizeof(acpi_madt_t); - + memset((void *)madt, 0, sizeof(acpi_madt_t)); - + /* fill out header fields */ memcpy(header->signature, "APIC", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_madt_t); header->revision = 1; @@ -207,10 +207,10 @@ void acpi_create_madt(acpi_madt_t *madt) madt->flags = 0x1; /* PCAT_COMPAT */ current = acpi_fill_madt(current); - + /* recalculate length */ header->length= current - (unsigned long)madt; - + header->checksum = acpi_checksum((void *)madt, header->length); } @@ -219,23 +219,23 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) acpi_header_t *header=&(mcfg->header); unsigned long current=(unsigned long)mcfg+sizeof(acpi_mcfg_t); - + memset((void *)mcfg, 0, sizeof(acpi_mcfg_t)); - + /* fill out header fields */ memcpy(header->signature, "MCFG", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_mcfg_t); header->revision = 1; current = acpi_fill_mcfg(current); - + /* recalculate length */ header->length= current - (unsigned long)mcfg; - + header->checksum = acpi_checksum((void *)mcfg, header->length); } @@ -294,7 +294,7 @@ int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek,u32 sizek, u32 mem->proximity_domain = node; - mem->flags = flags; + mem->flags = flags; return(mem->length); } @@ -356,15 +356,15 @@ void acpi_create_hpet(acpi_hpet_t *hpet) #define HPET_ADDR 0xfed00000ULL acpi_header_t *header=&(hpet->header); acpi_addr_t *addr=&(hpet->addr); - + memset((void *)hpet, 0, sizeof(acpi_hpet_t)); - + /* fill out header fields */ memcpy(header->signature, "HPET", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_hpet_t); header->revision = 1; @@ -378,12 +378,12 @@ void acpi_create_hpet(acpi_hpet_t *hpet) hpet->id = 0x102282a0; /* AMD ? */ hpet->number = 0; hpet->min_tick = 4096; - + header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } void acpi_create_facs(acpi_facs_t *facs) { - + memset( (void *)facs,0, sizeof(acpi_facs_t)); memcpy(facs->signature, "FACS", 4); @@ -398,46 +398,46 @@ void acpi_create_facs(acpi_facs_t *facs) } void acpi_write_rsdt(acpi_rsdt_t *rsdt) -{ +{ acpi_header_t *header=&(rsdt->header); - + /* fill out header fields */ memcpy(header->signature, "RSDT", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_rsdt_t); header->revision = 1; - + /* fill out entries */ // entries are filled in later, we come with an empty set. - + /* fix checksum */ - + header->checksum = acpi_checksum((void *)rsdt, sizeof(acpi_rsdt_t)); } void acpi_write_xsdt(acpi_xsdt_t *xsdt) -{ +{ acpi_header_t *header=&(xsdt->header); - + /* fill out header fields */ memcpy(header->signature, "XSDT", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); - + header->length = sizeof(acpi_xsdt_t); header->revision = 1; - + /* fill out entries */ // entries are filled in later, we come with an empty set. - + /* fix checksum */ - + header->checksum = acpi_checksum((void *)xsdt, sizeof(acpi_xsdt_t)); } @@ -448,7 +448,7 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt) memcpy(rsdp->oem_id, OEM_ID, 6); rsdp->length = sizeof(acpi_rsdp_t); rsdp->rsdt_address = (u32)rsdt; - /* Some OSes expect an XSDT to be present for RSD PTR + /* Some OSes expect an XSDT to be present for RSD PTR * revisions >= 2. If we don't have an ACPI XSDT, force * ACPI 1.0 (and thus RSD PTR revision 0) */ @@ -547,7 +547,7 @@ void *acpi_find_wakeup_vector(void) printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp); rsdt = (acpi_rsdt_t *) rsdp->rsdt_address; - + end = (char *) rsdt + rsdt->header.length; printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end); diff --git a/src/arch/i386/boot/acpigen.c b/src/arch/i386/boot/acpigen.c index 3ed7a2f05d..2bd2ab5630 100644 --- a/src/arch/i386/boot/acpigen.c +++ b/src/arch/i386/boot/acpigen.c @@ -147,8 +147,8 @@ int acpigen_emit_stream(const char *data, int size) return size; } -/* The NameString are bit tricky, each element can be 4 chars, if - less its padded with underscore. Check 18.2.2 and 18.4 +/* The NameString are bit tricky, each element can be 4 chars, if + less its padded with underscore. Check 18.2.2 and 18.4 and 5.3 of ACPI specs 3.0 for details */ @@ -160,14 +160,14 @@ static int acpigen_emit_simple_namestring(const char *name) { len += acpigen_emit_stream(ud, 4 - i); break; } else { - len += acpigen_emit_byte(name[i]); + len += acpigen_emit_byte(name[i]); } } return len; } static int acpigen_emit_double_namestring(const char *name, int dotpos) { - int len = 0; + int len = 0; /* mark dual name prefix */ len += acpigen_emit_byte(0x2e); len += acpigen_emit_simple_namestring(name); @@ -177,7 +177,7 @@ static int acpigen_emit_double_namestring(const char *name, int dotpos) { static int acpigen_emit_multi_namestring(const char *name) { int len = 0, count = 0; - unsigned char *pathlen; + unsigned char *pathlen; /* mark multi name prefix */ len += acpigen_emit_byte(0x2f); len += acpigen_emit_byte(0x0); @@ -229,7 +229,7 @@ int acpigen_emit_namestring(const char *namepath) { if (dotcount == 0) { len += acpigen_emit_simple_namestring(namepath); - } else if (dotcount == 1) { + } else if (dotcount == 1) { len += acpigen_emit_double_namestring(namepath, dotpos); } else { len += acpigen_emit_multi_namestring(namepath); diff --git a/src/arch/i386/boot/boot.c b/src/arch/i386/boot/boot.c index 895065e64a..d9cb02e776 100644 --- a/src/arch/i386/boot/boot.c +++ b/src/arch/i386/boot/boot.c @@ -63,9 +63,9 @@ int elf_check_arch(Elf_ehdr *ehdr) return ( ((ehdr->e_machine == EM_386) || (ehdr->e_machine == EM_486)) && (ehdr->e_ident[EI_CLASS] == ELFCLASS32) && - (ehdr->e_ident[EI_DATA] == ELFDATA2LSB) + (ehdr->e_ident[EI_DATA] == ELFDATA2LSB) ); - + } void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) @@ -74,7 +74,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) unsigned long lb_start, lb_size; unsigned long adjust, adjusted_boot_notes; - elf_boot_notes.hdr.b_checksum = + elf_boot_notes.hdr.b_checksum = compute_ip_checksum(&elf_boot_notes, sizeof(elf_boot_notes)); lb_start = (unsigned long)&_ram_seg; @@ -82,7 +82,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) adjust = buffer + size - lb_start; adjusted_boot_notes = (unsigned long)&elf_boot_notes; - adjusted_boot_notes += adjust; + adjusted_boot_notes += adjust; printk(BIOS_SPEW, "entry = 0x%08lx\n", (unsigned long)entry); printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start); @@ -91,7 +91,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) printk(BIOS_SPEW, "buffer = 0x%08lx\n", buffer); printk(BIOS_SPEW, " elf_boot_notes = 0x%08lx\n", (unsigned long)&elf_boot_notes); printk(BIOS_SPEW, "adjusted_boot_notes = 0x%08lx\n", adjusted_boot_notes); - + /* Jump to kernel */ __asm__ __volatile__( " cld \n\t" @@ -172,7 +172,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) " popl %%edi\n\t" " popl %%esi\n\t" - :: + :: "ri" (lb_start), "ri" (buffer), "ri" (lb_size), "ri" (entry), #if CONFIG_MULTIBOOT diff --git a/src/arch/i386/boot/coreboot_table.c b/src/arch/i386/boot/coreboot_table.c index b88ca1adba..bdf3b1bc6a 100644 --- a/src/arch/i386/boot/coreboot_table.c +++ b/src/arch/i386/boot/coreboot_table.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2003-2004 Eric Biederman * Copyright (C) 2005-2010 coresystems GmbH * @@ -71,7 +71,7 @@ static struct lb_record *lb_last_record(struct lb_header *header) #if 0 static struct lb_record *lb_next_record(struct lb_record *rec) { - rec = (void *)(((char *)rec) + rec->size); + rec = (void *)(((char *)rec) + rec->size); return rec; } #endif @@ -173,7 +173,7 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header) mainboard->tag = LB_TAG_MAINBOARD; mainboard->size = (sizeof(*mainboard) + - strlen(mainboard_vendor) + 1 + + strlen(mainboard_vendor) + 1 + strlen(mainboard_part_number) + 1 + 3) & ~3; @@ -203,7 +203,7 @@ static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) cmos_checksum->range_end = ( LB_CKS_RANGE_END * 8 ) + 7; cmos_checksum->location = LB_CKS_LOC * 8; cmos_checksum->type = CHECKSUM_PCBIOS; - + return cmos_checksum; } #endif @@ -320,7 +320,7 @@ static void lb_cleanup_memory_ranges(struct lb_memory *mem) int entries; int i, j; entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - + /* Sort the lb memory ranges */ for(i = 0; i < entries; i++) { uint64_t entry_start = unpack_lb64(mem->map[i].start); @@ -357,17 +357,17 @@ static void lb_cleanup_memory_ranges(struct lb_memory *mem) mem->map[i].size = pack_lb64(end - start); /* Delete the entry I have merged with */ - memmove(&mem->map[i + 1], &mem->map[i + 2], + memmove(&mem->map[i + 1], &mem->map[i + 2], ((entries - i - 2) * sizeof(mem->map[0]))); mem->size -= sizeof(mem->map[0]); entries -= 1; /* See if I can merge with the next entry as well */ - i -= 1; + i -= 1; } } } -static void lb_remove_memory_range(struct lb_memory *mem, +static void lb_remove_memory_range(struct lb_memory *mem, uint64_t start, uint64_t size) { uint64_t end; @@ -383,16 +383,16 @@ static void lb_remove_memory_range(struct lb_memory *mem, uint64_t map_end = map_start + unpack_lb64(mem->map[i].size); if ((start <= map_start) && (end >= map_end)) { /* Remove the completely covered range */ - memmove(&mem->map[i], &mem->map[i + 1], + memmove(&mem->map[i], &mem->map[i + 1], ((entries - i - 1) * sizeof(mem->map[0]))); mem->size -= sizeof(mem->map[0]); entries -= 1; /* Since the index will disappear revisit what will appear here */ - i -= 1; + i -= 1; } else if ((start > map_start) && (end < map_end)) { /* Split the memory range */ - memmove(&mem->map[i + 1], &mem->map[i], + memmove(&mem->map[i + 1], &mem->map[i], ((entries - i) * sizeof(mem->map[0]))); mem->size += sizeof(mem->map[0]); entries += 1; @@ -430,7 +430,7 @@ static void lb_dump_memory_ranges(struct lb_memory *mem) int entries; int i; entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); - + printk(BIOS_DEBUG, "coreboot memory table:\n"); for(i = 0; i < entries; i++) { uint64_t entry_start = unpack_lb64(mem->map[i].start); @@ -448,14 +448,14 @@ static void lb_dump_memory_ranges(struct lb_memory *mem) default: entry_type="UNKNOWN!"; break; } - printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", + printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", i, entry_start, entry_start+entry_size-1, entry_type); - + } } -/* Routines to extract part so the coreboot table or +/* Routines to extract part so the coreboot table or * information from the coreboot table after we have written it. * Currently get_lb_mem relies on a global we can change the * implementaiton. @@ -492,8 +492,8 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) extern uint64_t high_tables_base, high_tables_size; #endif -unsigned long write_coreboot_table( - unsigned long low_table_start, unsigned long low_table_end, +unsigned long write_coreboot_table( + unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) { struct lb_header *head; @@ -509,7 +509,7 @@ unsigned long write_coreboot_table( printk(BIOS_DEBUG, "New low_table_end: 0x%08lx\n", low_table_end); printk(BIOS_DEBUG, "Now going to write high coreboot table at 0x%08lx\n", rom_table_end); - + head = lb_table_init(rom_table_end); rom_table_end = (unsigned long)head; printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); @@ -523,7 +523,7 @@ unsigned long write_coreboot_table( low_table_end = (unsigned long)head; } #endif - + printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end); low_table_end += 0xfff; // 4K aligned low_table_end &= ~0xfff; @@ -535,7 +535,7 @@ unsigned long write_coreboot_table( rom_table_end &= ~0xffff; printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end); -#if (CONFIG_HAVE_OPTION_TABLE == 1) +#if (CONFIG_HAVE_OPTION_TABLE == 1) { struct lb_record *rec_dest = lb_new_record(head); /* Copy the option config table, it's already a lb_record... */ @@ -546,9 +546,9 @@ unsigned long write_coreboot_table( #endif /* Record where RAM is located */ mem = build_lb_mem(head); - + /* Record the mptable and the the lb_table (This will be adjusted later) */ - lb_add_memory_range(mem, LB_MEM_TABLE, + lb_add_memory_range(mem, LB_MEM_TABLE, low_table_start, low_table_end - low_table_start); /* Record the pirq table, acpi tables, and maybe the mptable */ @@ -588,5 +588,5 @@ unsigned long write_coreboot_table( /* Remember where my valid memory ranges are */ return lb_table_fini(head, 1); - + } diff --git a/src/arch/i386/boot/mpspec.c b/src/arch/i386/boot/mpspec.c index 1beba873cc..47ad8ccb33 100644 --- a/src/arch/i386/boot/mpspec.c +++ b/src/arch/i386/boot/mpspec.c @@ -31,7 +31,7 @@ void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_ph { struct intel_mp_floating *mf; void *v; - + v = (void *)addr; mf = v; mf->mpf_signature[0] = '_'; @@ -106,7 +106,7 @@ void smp_write_processors(struct mp_config_table *mc) unsigned cpu_feature_flags; struct cpuid_result result; device_t cpu; - + boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; result = cpuid(1); @@ -114,7 +114,7 @@ void smp_write_processors(struct mp_config_table *mc) cpu_feature_flags = result.edx; for(cpu = all_devices; cpu; cpu = cpu->next) { unsigned long cpu_flag; - if ((cpu->path.type != DEVICE_PATH_APIC) || + if ((cpu->path.type != DEVICE_PATH_APIC) || (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { continue; @@ -126,7 +126,7 @@ void smp_write_processors(struct mp_config_table *mc) if (boot_apic_id == cpu->path.apic.apic_id) { cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; } - smp_write_processor(mc, + smp_write_processor(mc, cpu->path.apic.apic_id, apic_version, cpu_flag, cpu_features, cpu_feature_flags ); @@ -146,7 +146,7 @@ void smp_write_bus(struct mp_config_table *mc, } void smp_write_ioapic(struct mp_config_table *mc, - unsigned char id, unsigned char ver, + unsigned char id, unsigned char ver, unsigned long apicaddr) { struct mpc_config_ioapic *mpc; diff --git a/src/arch/i386/boot/pirq_routing.c b/src/arch/i386/boot/pirq_routing.c index 86a3500444..4873f6d751 100644 --- a/src/arch/i386/boot/pirq_routing.c +++ b/src/arch/i386/boot/pirq_routing.c @@ -26,7 +26,7 @@ static void check_pirq_routing_table(struct irq_routing_table *rt) printk(BIOS_DEBUG, "%s(): Interrupt Routing Table located at %p.\n", __func__, addr); - + sum = rt->checksum - sum; if (sum != rt->checksum) { @@ -72,9 +72,9 @@ static int verify_copy_pirq_routing_table(unsigned long addr) } } printk(BIOS_INFO, "done\n"); - + check_pirq_routing_table((struct irq_routing_table *)addr); - + return 0; } #endif diff --git a/src/arch/i386/boot/tables.c b/src/arch/i386/boot/tables.c index 76a7bb21b1..6ee7c2c876 100644 --- a/src/arch/i386/boot/tables.c +++ b/src/arch/i386/boot/tables.c @@ -60,12 +60,12 @@ struct lb_memory *write_tables(void) printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); - rom_table_start = 0xf0000; + rom_table_start = 0xf0000; rom_table_end = 0xf0000; /* Start low addr at 0x500, so we don't run into conflicts with the BDA * in case our data structures grow beyound 0x400. Only multiboot, GDT - * and the coreboot table use low_tables. + * and the coreboot table use low_tables. */ low_table_start = 0; low_table_end = 0x500; @@ -126,7 +126,7 @@ struct lb_memory *write_tables(void) /* Write ACPI tables to F segment and high tables area */ /* Ok, this is a bit hacky still, because some day we want to have this - * completely dynamic. But right now we are setting fixed sizes. + * completely dynamic. But right now we are setting fixed sizes. * It's probably still better than the old high_table_base code because * now at least we know when we have an overflow in the area. * @@ -213,7 +213,7 @@ struct lb_memory *write_tables(void) write_coreboot_table(low_table_start, low_table_end, rom_table_start, rom_table_end); } - + post_code(0x9e); #if CONFIG_HAVE_ACPI_RESUME @@ -223,7 +223,7 @@ struct lb_memory *write_tables(void) */ cbmem_add(CBMEM_ID_RESUME, 1024 * (1024-64)); #endif - + // Remove before sending upstream cbmem_list(); diff --git a/src/arch/i386/boot/wakeup.S b/src/arch/i386/boot/wakeup.S index b348e95a71..a1df4d5597 100644 --- a/src/arch/i386/boot/wakeup.S +++ b/src/arch/i386/boot/wakeup.S @@ -68,11 +68,11 @@ __wakeup: * protected mode is turned off. */ mov $0x30, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss /* Turn off protection */ movl %cr0, %eax diff --git a/src/arch/i386/coreboot_ram.ld b/src/arch/i386/coreboot_ram.ld index 67c78cecbc..2e602205dd 100644 --- a/src/arch/i386/coreboot_ram.ld +++ b/src/arch/i386/coreboot_ram.ld @@ -59,7 +59,7 @@ SECTIONS . = ALIGN(4); _erodata = .; - } + } /* After the code we place initialized data (typically initialized * global variables). This gets copied into ram by startup code. * __data_start and __data_end shows where in ram this should be placed, @@ -113,11 +113,11 @@ SECTIONS /* Avoid running into 0xa0000-0xfffff */ _bogus = ASSERT(CONFIG_RAMBASE >= 0x100000 || _eheap < 0xa0000, "Please move RAMBASE to 1MB"); - /* The ram segment. This includes all memory used by the memory + /* The ram segment. This includes all memory used by the memory * resident copy of coreboot, except the tables that are produced on * the fly, but including stack and heap. */ - _ram_seg = _text; + _ram_seg = _text; _eram_seg = _eheap; /* CONFIG_RAMTOP is the upper address of cached memory (among other diff --git a/src/arch/i386/include/arch/acpi.h b/src/arch/i386/include/arch/acpi.h index ebab54ca42..9b1e1a5d9e 100644 --- a/src/arch/i386/include/arch/acpi.h +++ b/src/arch/i386/include/arch/acpi.h @@ -30,7 +30,7 @@ #if CONFIG_GENERATE_ACPI_TABLES==1 #include - + #define RSDP_SIG "RSD PTR " /* RSDT Pointer signature */ #define ACPI_TABLE_CREATOR "COREBOOT" #define OEM_ID "CORE " diff --git a/src/arch/i386/include/arch/coreboot_tables.h b/src/arch/i386/include/arch/coreboot_tables.h index 91e6d6cbd5..3c9bf98f22 100644 --- a/src/arch/i386/include/arch/coreboot_tables.h +++ b/src/arch/i386/include/arch/coreboot_tables.h @@ -8,7 +8,7 @@ unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end); -void lb_memory_range(struct lb_memory *mem, +void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); /* Routines to extract part so the coreboot table or information diff --git a/src/arch/i386/include/arch/cpu.h b/src/arch/i386/include/arch/cpu.h index 30b6cc300b..3e799f014d 100644 --- a/src/arch/i386/include/arch/cpu.h +++ b/src/arch/i386/include/arch/cpu.h @@ -102,7 +102,7 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_RISE 7 #define X86_VENDOR_TRANSMETA 8 #define X86_VENDOR_NSC 9 -#define X86_VENDOR_SIS 10 +#define X86_VENDOR_SIS 10 #define X86_VENDOR_UNKNOWN 0xff #if !defined(__PRE_RAM__) @@ -129,8 +129,8 @@ static inline struct cpu_info *cpu_info(void) struct cpu_info *ci; __asm__("andl %%esp,%0; " "orl %2, %0 " - :"=r" (ci) - : "0" (~(CONFIG_STACK_SIZE - 1)), + :"=r" (ci) + : "0" (~(CONFIG_STACK_SIZE - 1)), "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) ); return ci; diff --git a/src/arch/i386/include/arch/io.h b/src/arch/i386/include/arch/io.h index 3a76579fbc..dd8d647380 100644 --- a/src/arch/i386/include/arch/io.h +++ b/src/arch/i386/include/arch/io.h @@ -82,7 +82,7 @@ static inline uint32_t inl(uint16_t port) static inline void outsb(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsb " + "cld ; rep ; outsb " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -91,7 +91,7 @@ static inline void outsb(uint16_t port, const void *addr, unsigned long count) static inline void outsw(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsw " + "cld ; rep ; outsw " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -100,7 +100,7 @@ static inline void outsw(uint16_t port, const void *addr, unsigned long count) static inline void outsl(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsl " + "cld ; rep ; outsl " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -110,7 +110,7 @@ static inline void outsl(uint16_t port, const void *addr, unsigned long count) static inline void insb(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insb " + "cld ; rep ; insb " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -119,7 +119,7 @@ static inline void insb(uint16_t port, void *addr, unsigned long count) static inline void insw(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insw " + "cld ; rep ; insw " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -128,7 +128,7 @@ static inline void insw(uint16_t port, void *addr, unsigned long count) static inline void insl(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insl " + "cld ; rep ; insl " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); diff --git a/src/arch/i386/include/arch/pciconf.h b/src/arch/i386/include/arch/pciconf.h index 09133b5567..a35693519e 100644 --- a/src/arch/i386/include/arch/pciconf.h +++ b/src/arch/i386/include/arch/pciconf.h @@ -1,7 +1,7 @@ #ifndef PCI_CONF_REG_INDEX // These are defined in the PCI spec, and hence are theoretically -// inclusive of ANYTHING that uses a PCI bus. +// inclusive of ANYTHING that uses a PCI bus. #define PCI_CONF_REG_INDEX 0xcf8 #define PCI_CONF_REG_DATA 0xcfc diff --git a/src/arch/i386/include/arch/registers.h b/src/arch/i386/include/arch/registers.h index 63aeec826b..bc1b681339 100644 --- a/src/arch/i386/include/arch/registers.h +++ b/src/arch/i386/include/arch/registers.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h index d69d4541bc..f1466273d8 100644 --- a/src/arch/i386/include/arch/romcc_io.h +++ b/src/arch/i386/include/arch/romcc_io.h @@ -85,7 +85,7 @@ static inline int log2f(int value) typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ -/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, +/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access */ @@ -303,7 +303,7 @@ static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); - + for(; dev <=last; dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); diff --git a/src/arch/i386/include/arch/smp/atomic.h b/src/arch/i386/include/arch/smp/atomic.h index 7061461d33..18bbae27cb 100644 --- a/src/arch/i386/include/arch/smp/atomic.h +++ b/src/arch/i386/include/arch/smp/atomic.h @@ -18,29 +18,29 @@ typedef struct { volatile int counter; } atomic_t; /** * atomic_read - read atomic variable * @v: pointer of type atomic_t - * + * * Atomically reads the value of @v. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_read(v) ((v)->counter) /** * atomic_set - set atomic variable * @v: pointer of type atomic_t * @i: required value - * + * * Atomically sets the value of @v to @i. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_set(v,i) (((v)->counter) = (i)) /** * atomic_inc - increment atomic variable * @v: pointer of type atomic_t - * + * * Atomically increments @v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ static __inline__ __attribute__((always_inline)) void atomic_inc(atomic_t *v) { __asm__ __volatile__( @@ -52,10 +52,10 @@ static __inline__ __attribute__((always_inline)) void atomic_inc(atomic_t *v) /** * atomic_dec - decrement atomic variable * @v: pointer of type atomic_t - * + * * Atomically decrements @v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ static __inline__ __attribute__((always_inline)) void atomic_dec(atomic_t *v) { __asm__ __volatile__( diff --git a/src/arch/i386/include/arch/smp/mpspec.h b/src/arch/i386/include/arch/smp/mpspec.h index ab29f2a088..1645d3b38f 100644 --- a/src/arch/i386/include/arch/smp/mpspec.h +++ b/src/arch/i386/include/arch/smp/mpspec.h @@ -9,9 +9,9 @@ /* * This tag identifies where the SMP configuration - * information is. + * information is. */ - + #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_') /* @@ -72,7 +72,7 @@ struct mpc_config_processor unsigned char mpc_cpuflag; #define MPC_CPU_ENABLED 1 /* Processor is available */ #define MPC_CPU_BOOTPROCESSOR 2 /* Processor is the BP */ - unsigned long mpc_cpufeature; + unsigned long mpc_cpufeature; #define MPC_CPU_STEPPING_MASK 0x0F #define MPC_CPU_MODEL_MASK 0xF0 #define MPC_CPU_FAMILY_MASK 0xF00 @@ -140,7 +140,7 @@ struct mpc_config_lintsrc unsigned short mpc_irqflag; unsigned char mpc_srcbusid; unsigned char mpc_srcbusirq; - unsigned char mpc_destapic; + unsigned char mpc_destapic; #define MP_APIC_ALL 0xFF unsigned char mpc_destapiclint; } __attribute__((packed)); @@ -211,7 +211,7 @@ struct mp_exten_compatibility_address_space { #define ADDRESS_RANGE_SUBTRACT 1 #define ADDRESS_RANGE_ADD 0 unsigned int mpe_range_list; -#define RANGE_LIST_IO_ISA 0 +#define RANGE_LIST_IO_ISA 0 /* X100 - X3FF * X500 - X7FF * X900 - XBFF @@ -243,7 +243,7 @@ void smp_write_processors(struct mp_config_table *mc); void smp_write_bus(struct mp_config_table *mc, unsigned char id, const char *bustype); void smp_write_ioapic(struct mp_config_table *mc, - unsigned char id, unsigned char ver, + unsigned char id, unsigned char ver, unsigned long apicaddr); void smp_write_intsrc(struct mp_config_table *mc, unsigned char irqtype, unsigned short irqflag, @@ -269,7 +269,7 @@ void smp_write_compatibility_address_space(struct mp_config_table *mc, unsigned int range_list); unsigned char smp_compute_checksum(void *v, int len); void *smp_write_floating_table(unsigned long addr); -void *smp_write_floating_table_physaddr(unsigned long addr, +void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_physptr); unsigned long write_smp_table(unsigned long addr); diff --git a/src/arch/i386/include/bitops.h b/src/arch/i386/include/bitops.h index fae2045b9a..9206465c77 100644 --- a/src/arch/i386/include/bitops.h +++ b/src/arch/i386/include/bitops.h @@ -15,6 +15,6 @@ static inline unsigned long log2(unsigned long x) "1:\n\t" : "=r" (r) : "r" (x)); return r; - + } #endif /* I386_BITOPS_H */ diff --git a/src/arch/i386/include/stdint.h b/src/arch/i386/include/stdint.h index a015a84b2a..b393cc10e0 100644 --- a/src/arch/i386/include/stdint.h +++ b/src/arch/i386/include/stdint.h @@ -9,7 +9,7 @@ /* Exact integral types */ typedef unsigned char uint8_t; -typedef signed char int8_t; +typedef signed char int8_t; typedef unsigned short uint16_t; typedef signed short int16_t; @@ -24,7 +24,7 @@ typedef signed long long int64_t; /* Small types */ typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; +typedef signed char int_least8_t; typedef unsigned short uint_least16_t; typedef signed short int_least16_t; @@ -39,7 +39,7 @@ typedef signed long long int_least64_t; /* Fast Types */ typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; +typedef signed char int_fast8_t; typedef unsigned int uint_fast16_t; typedef signed int int_fast16_t; @@ -50,7 +50,7 @@ typedef signed int int_fast32_t; #if __HAVE_LONG_LONG__ typedef unsigned long long uint_fast64_t; typedef signed long long int_fast64_t; -#endif +#endif /* Types for `void *' pointers. */ typedef int intptr_t; diff --git a/src/arch/i386/init/bootblock_prologue.c b/src/arch/i386/init/bootblock_prologue.c index b07aec3524..25da7b769f 100644 --- a/src/arch/i386/init/bootblock_prologue.c +++ b/src/arch/i386/init/bootblock_prologue.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2002 Eric Biederman * * This program is free software; you can redistribute it and/or modify diff --git a/src/arch/i386/init/crt0_prologue.inc b/src/arch/i386/init/crt0_prologue.inc index 225a003d8f..8947f20de3 100644 --- a/src/arch/i386/init/crt0_prologue.inc +++ b/src/arch/i386/init/crt0_prologue.inc @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2002 Eric Biederman * * This program is free software; you can redistribute it and/or modify diff --git a/src/arch/i386/init/crt0_romcc_epilogue.inc b/src/arch/i386/init/crt0_romcc_epilogue.inc index 73107c913b..3bd1b36992 100644 --- a/src/arch/i386/init/crt0_romcc_epilogue.inc +++ b/src/arch/i386/init/crt0_romcc_epilogue.inc @@ -1,4 +1,4 @@ -/* +/* * Copyright 2002 Eric Biederman * * This file is free software; you can redistribute it and/or @@ -11,7 +11,7 @@ __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -19,7 +19,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/arch/i386/init/ldscript.ld b/src/arch/i386/init/ldscript.ld index e56f644034..149f048638 100644 --- a/src/arch/i386/init/ldscript.ld +++ b/src/arch/i386/init/ldscript.ld @@ -35,6 +35,6 @@ SECTIONS { *(.reset) . = 15 ; BYTE(0x00); - } + } } diff --git a/src/arch/i386/lib/cbfs_and_run.c b/src/arch/i386/lib/cbfs_and_run.c index a6f19e50ee..1b86f56371 100644 --- a/src/arch/i386/lib/cbfs_and_run.c +++ b/src/arch/i386/lib/cbfs_and_run.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2008-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/arch/i386/lib/cpu.c b/src/arch/i386/lib/cpu.c index 0e54b9a87d..3732ae296e 100644 --- a/src/arch/i386/lib/cpu.c +++ b/src/arch/i386/lib/cpu.c @@ -43,7 +43,7 @@ static int have_cpuid_p(void) * by the fact that they preserve the flags across the division of 5/2. * PII and PPro exhibit this behavior too, but they have cpuid available. */ - + /* * Perform the Cyrix 5/2 test. A Cyrix won't change * the flags, while other 486 chips will. @@ -68,11 +68,11 @@ static inline int test_cyrix_52div(void) * Detect a NexGen CPU running without BIOS hypercode new enough * to have CPUID. (Thanks to Herbert Oppmann) */ - + static int deep_magic_nexgen_probe(void) { int ret; - + __asm__ __volatile__ ( " movw $0x5555, %%ax\n" " xorw %%dx,%%dx\n" @@ -81,7 +81,7 @@ static int deep_magic_nexgen_probe(void) " movl $0, %%eax\n" " jnz 1f\n" " movl $1, %%eax\n" - "1:\n" + "1:\n" : "=a" (ret) : : "cx", "dx" ); return ret; } @@ -95,7 +95,7 @@ static struct { } x86_vendors[] = { { X86_VENDOR_INTEL, "GenuineIntel", }, { X86_VENDOR_CYRIX, "CyrixInstead", }, - { X86_VENDOR_AMD, "AuthenticAMD", }, + { X86_VENDOR_AMD, "AuthenticAMD", }, { X86_VENDOR_UMC, "UMC UMC UMC ", }, { X86_VENDOR_NEXGEN, "NexGenDriven", }, { X86_VENDOR_CENTAUR, "CentaurHauls", }, @@ -124,7 +124,7 @@ static const char *cpu_vendor_name(int vendor) const char *name; name = ""; if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && - (x86_vendor_name[vendor] != 0)) + (x86_vendor_name[vendor] != 0)) { name = x86_vendor_name[vendor]; } @@ -173,7 +173,7 @@ static void identify_cpu(struct device *cpu) vendor_name[10] = (result.ecx >> 16) & 0xff; vendor_name[11] = (result.ecx >> 24) & 0xff; vendor_name[12] = '\0'; - + /* Intel-defined flags: level 0x00000001 */ if (cpuid_level >= 0x00000001) { cpu->device = cpuid_eax(0x00000001); @@ -200,7 +200,7 @@ static void set_cpu_ops(struct device *cpu) struct cpu_device_id *id; for(id = driver->id_table; id->vendor != X86_VENDOR_INVALID; id++) { if ((cpu->vendor == id->vendor) && - (cpu->device == id->device)) + (cpu->device == id->device)) { goto found; } @@ -221,7 +221,7 @@ void cpu_initialize(void) struct device *cpu; struct cpu_info *info; struct cpuinfo_x86 c; - + info = cpu_info(); printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index); @@ -240,11 +240,11 @@ void cpu_initialize(void) printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask); - + /* Lookup the cpu's operations */ set_cpu_ops(cpu); - if(!cpu->ops) { + if(!cpu->ops) { /* mask out the stepping and try again */ cpu->device -= c.x86_mask; set_cpu_ops(cpu); @@ -252,7 +252,7 @@ void cpu_initialize(void) if(!cpu->ops) die("Unknown cpu"); printk(BIOS_DEBUG, "Using generic cpu ops (good)\n"); } - + /* Initialize the cpu */ if (cpu->ops && cpu->ops->init) { diff --git a/src/arch/i386/lib/exception.c b/src/arch/i386/lib/exception.c index eb1df20e26..20917b6f40 100644 --- a/src/arch/i386/lib/exception.c +++ b/src/arch/i386/lib/exception.c @@ -4,7 +4,7 @@ #if defined(CONFIG_GDB_STUB) && CONFIG_GDB_STUB == 1 /* BUFMAX defines the maximum number of characters in inbound/outbound buffers. - * At least NUM_REGBYTES*2 are needed for register packets + * At least NUM_REGBYTES*2 are needed for register packets */ #define BUFMAX 400 enum regnames { @@ -62,7 +62,7 @@ static uint32_t gdb_stub_registers[NUM_REGS]; #define GDB_SIGSOUND 42 /* Sound completed */ #define GDB_SIGSAK 43 /* Secure attention */ #define GDB_SIGPRIO 44 /* SIGPRIO */ - + #define GDB_SIG33 45 /* Real-time event 33 */ #define GDB_SIG34 46 /* Real-time event 34 */ #define GDB_SIG35 47 /* Real-time event 35 */ @@ -375,7 +375,7 @@ void x86_exception(struct eregs *info) if (info->vector < ARRAY_SIZE(exception_to_signal)) { signo = exception_to_signal[info->vector]; } - + /* reply to the host that an exception has occured */ out_buffer[0] = 'S'; out_buffer[1] = hexchars[(signo>>4) & 0xf]; @@ -412,7 +412,7 @@ void x86_exception(struct eregs *info) case 'm': /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */ ptr = &in_buffer[1]; - if ( parse_ulong(&ptr, &addr) && + if ( parse_ulong(&ptr, &addr) && (*ptr++ == ',') && parse_ulong(&ptr, &length)) { copy_to_hex(out_buffer, (void *)addr, length); @@ -423,7 +423,7 @@ void x86_exception(struct eregs *info) case 'M': /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */ ptr = &in_buffer[1]; - if ( parse_ulong(&ptr, &addr) && + if ( parse_ulong(&ptr, &addr) && (*(ptr++) == ',') && parse_ulong(&ptr, &length) && (*(ptr++) == ':')) { @@ -475,7 +475,7 @@ void x86_exception(struct eregs *info) put_packet(out_buffer); } #else /* !CONFIG_GDB_STUB */ - printk(BIOS_EMERG, + printk(BIOS_EMERG, "Unexpected Exception: %d @ %02x:%08x - Halting\n" "Code: %d eflags: %08x\n" "eax: %08x ebx: %08x ecx: %08x edx: %08x\n" diff --git a/src/arch/i386/lib/id.inc b/src/arch/i386/lib/id.inc index 9f402f85b0..443dbad38a 100644 --- a/src/arch/i386/lib/id.inc +++ b/src/arch/i386/lib/id.inc @@ -2,9 +2,9 @@ .globl __id_start __id_start: -vendor: +vendor: .asciz CONFIG_MAINBOARD_VENDOR -part: +part: .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */ .long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */ diff --git a/src/arch/i386/lib/ioapic.c b/src/arch/i386/lib/ioapic.c index efc2ac52fc..d6616f5529 100644 --- a/src/arch/i386/lib/ioapic.c +++ b/src/arch/i386/lib/ioapic.c @@ -40,13 +40,13 @@ void clear_ioapic(u32 ioapic_base) u32 low, high; u32 i, ioapic_interrupts; - printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); + printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); /* Read the available number of interrupts */ ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; if (!ioapic_interrupts || ioapic_interrupts == 0xff) ioapic_interrupts = 24; - printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); + printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); low = DISABLED; high = NONE; @@ -70,15 +70,15 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) u32 low, high; u32 i, ioapic_interrupts; - printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = %02x\n", bsp_lapicid); if (ioapic_id) { - printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); + printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); /* Set IOAPIC ID if it has been specified */ - io_apic_write(ioapic_base, 0x00, - (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) | + io_apic_write(ioapic_base, 0x00, + (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) | (ioapic_id << 24)); } @@ -86,7 +86,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; if (!ioapic_interrupts || ioapic_interrupts == 0xff) ioapic_interrupts = 24; - printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); + printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); // XXX this decision should probably be made elsewhere, and @@ -101,11 +101,11 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) /* For the Pentium 4 and above APICs deliver their interrupts * on the front side bus, enable that. */ - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); #endif #ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); #endif diff --git a/src/arch/i386/lib/pci_ops_auto.c b/src/arch/i386/lib/pci_ops_auto.c index 1f144381ee..92eedd30fb 100644 --- a/src/arch/i386/lib/pci_ops_auto.c +++ b/src/arch/i386/lib/pci_ops_auto.c @@ -33,7 +33,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o) vendor = o->read16(&pbus, bus, devfn, PCI_VENDOR_ID); if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) || ((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) || - (vendor == PCI_VENDOR_ID_MOTOROLA))) { + (vendor == PCI_VENDOR_ID_MOTOROLA))) { return 1; } } @@ -54,8 +54,8 @@ static const struct pci_bus_operations *pci_check_direct(void) outb(0x01, 0xCFB); tmp = inl(0xCF8); outl(0x80000000, 0xCF8); - if ((inl(0xCF8) == 0x80000000) && - pci_sanity_check(&pci_cf8_conf1)) + if ((inl(0xCF8) == 0x80000000) && + pci_sanity_check(&pci_cf8_conf1)) { outl(tmp, 0xCF8); printk(BIOS_DEBUG, "PCI: Using configuration type 1\n"); diff --git a/src/arch/i386/lib/printk_init.c b/src/arch/i386/lib/printk_init.c index d3064046f7..f29ba667f1 100644 --- a/src/arch/i386/lib/printk_init.c +++ b/src/arch/i386/lib/printk_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of diff --git a/src/arch/i386/lib/stages.c b/src/arch/i386/lib/stages.c index 0605abf49b..a6a232a04a 100644 --- a/src/arch/i386/lib/stages.c +++ b/src/arch/i386/lib/stages.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2010 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/arch/i386/llshell/console.inc b/src/arch/i386/llshell/console.inc index 394d5c4f68..84f62e3448 100644 --- a/src/arch/i386/llshell/console.inc +++ b/src/arch/i386/llshell/console.inc @@ -149,7 +149,7 @@ jmp console0 jz 11f ; \ __CONSOLE_INLINE_TX_AL ; \ jmp 10b ; \ -11: +11: #define CONSOLE_EMERG_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) @@ -234,7 +234,7 @@ jmp console0 #define CONSOLE_SPEW_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) /* uses: esp, ax, dx */ -console_tx_al: +console_tx_al: __CONSOLE_INLINE_TX_AL RETSP @@ -333,7 +333,7 @@ console_tx_string: cmp $0, %al jne 9f RETSP -9: +9: __CONSOLE_INLINE_TX_AL jmp console_tx_string diff --git a/src/arch/i386/llshell/llshell.inc b/src/arch/i386/llshell/llshell.inc index 6f8996717a..a66ac150b5 100644 --- a/src/arch/i386/llshell/llshell.inc +++ b/src/arch/i386/llshell/llshell.inc @@ -27,16 +27,16 @@ jmp llshell_out // Designed to be an interactive shell that operates with zero // system resources. For example at initial boot. -// to use, jump to label "low_level_shell" +// to use, jump to label "low_level_shell" // set %esp to the return address for exiting -#define UART_BASEADDR $0x3f8 +#define UART_BASEADDR $0x3f8 #define resultreg %esi #define subroutinereg %edi #define freqtime $2193 // 1.93 * freq #define timertime $6000 -.equ sys_IOPL, 110 +.equ sys_IOPL, 110 // .data // .text @@ -75,9 +75,9 @@ cmds: \r\nAll values in hex (0x prefixing ok) \ \r\n" -cr: +cr: .string "\r\n" -spaces: +spaces: .string " " // .globl _start @@ -187,7 +187,7 @@ jz wmemw cmp $0x00776d6c,%eax jz wmeml cmp $0x0000646d,%eax -jz dodmem +jz dodmem cmp $0x6d656d74,%eax jz memt // mem test cmp $0x00727374,%eax @@ -195,7 +195,7 @@ jz rst // reset cmp $0x00525354,%eax jz RST cmp $0x62656570,%eax -jz beep +jz beep cmp $0x0000646c,%eax jz dodl // download to mem cmp $0x006a6d70,%eax @@ -203,7 +203,7 @@ jz jmpto // jump to location (eax holds return addr) cmp $0x62617564,%eax jz baud // change baudrate cmp $0x00696e74,%eax -jz doint // trigger an interrupt +jz doint // trigger an interrupt cmp $0x63616c6c,%eax jz callto // call assumes memory cmp $0x70757368,%eax @@ -270,7 +270,7 @@ processchar: cmp $0x3A,%al jl subnum cmp $0x47,%al -jl subcaps +jl subcaps //sublc: sub $0x57,%al jmp additupn @@ -370,7 +370,7 @@ jmp displaystring doneshow1: dec %cx cmp $0x0,%cx -jz exitdmem +jz exitdmem add $0x04,%ebx jmp dmemloop exitdmem: @@ -517,7 +517,7 @@ movl $int1a, subroutinereg jmp readnibbles int1a: mov resultreg,%eax -// need to lookup int table? +// need to lookup int table? // int %eax jmp readcommand @@ -560,7 +560,7 @@ jmp *subroutinereg displayhexlinear: mov resultreg,%eax -xchg %al,%ah +xchg %al,%ah rol $0x10,%eax xchg %al,%ah mov %eax,resultreg @@ -602,7 +602,7 @@ jmp *subroutinereg displayasciilinear: mov resultreg,%eax -xchg %al,%ah +xchg %al,%ah rol $0x10,%eax xchg %al,%ah mov %eax,resultreg diff --git a/src/arch/i386/llshell/pci.inc b/src/arch/i386/llshell/pci.inc index eb4d3c3845..7cb741008e 100644 --- a/src/arch/i386/llshell/pci.inc +++ b/src/arch/i386/llshell/pci.inc @@ -11,7 +11,7 @@ * * Notes: This routine is optimized for minimal register usage. * And the tricks it does cannot scale beyond writing a single byte. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the data byte @@ -52,7 +52,7 @@ * Effects: writes a single byte to pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant @@ -91,7 +91,7 @@ * Effects: writes a single byte to pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant @@ -118,7 +118,7 @@ - + /* * Macro: PCI_READ_CONFIG_BYTE * Arguments: %eax address to read from (includes bus, device, function, &offset) @@ -129,7 +129,7 @@ * Effects: reads a single byte from pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant @@ -165,7 +165,7 @@ * Effects: reads a 2 bytes from pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant @@ -201,7 +201,7 @@ * Effects: reads 4 bytes from pci config space * * Notes: This routine is optimized for minimal register usage. - * + * * What it does is almost simple. * It preserves %eax (baring special bits) until it is written * out to the appropriate port. And hides the least significant diff --git a/src/arch/i386/llshell/ramtest.inc b/src/arch/i386/llshell/ramtest.inc index 910f01608f..c02cf451ec 100644 --- a/src/arch/i386/llshell/ramtest.inc +++ b/src/arch/i386/llshell/ramtest.inc @@ -6,7 +6,7 @@ jmp rt_skip #define RAMTEST 1 -#if RAMTEST +#if RAMTEST .section ".rom.data" rt_test: .string "Testing SDRAM : " @@ -16,7 +16,7 @@ rt_toomany: .string "Too many errors.\r\n" rt_done: .string "Done.\r\n" .previous #endif - + ramtest: #if RAMTEST mov %eax, %esi @@ -41,7 +41,7 @@ ramtest: /* Display address being filled */ /* CONSOLE_INFO_TX_HEX32(arg) will overwrite %ebx with arg */ - + CONSOLE_INFO_TX_HEX32(%ebx) CONSOLE_INFO_TX_CHAR($'\r') 2: @@ -110,7 +110,7 @@ ramtest: sub $1, %ecx jz 5f jmp 3b -5: +5: CONSOLE_INFO_TX_STRING($rt_toomany) post_code(0xf1) jmp .Lhlt diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 686b09576f..061bffdad4 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -45,10 +45,10 @@ it with the version available from LANL. /** * @brief Main function of the RAM part of coreboot. * - * Coreboot is divided into Pre-RAM part and RAM part. - * + * Coreboot is divided into Pre-RAM part and RAM part. + * * Device Enumeration: - * In the dev_enumerate() phase, + * In the dev_enumerate() phase, */ void hardwaremain(int boot_complete); @@ -61,10 +61,10 @@ void hardwaremain(int boot_complete) /* console_init() MUST PRECEDE ALL printk()! */ console_init(); - + post_code(0x39); - printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", + printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", coreboot_version, coreboot_extra_version, coreboot_build, (boot_complete)?"rebooting":"booting"); @@ -76,7 +76,7 @@ void hardwaremain(int boot_complete) } /* FIXME: Is there a better way to handle this? */ - init_timer(); + init_timer(); /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); diff --git a/src/console/Kconfig b/src/console/Kconfig index 86d75754cd..b9d6f69253 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -98,7 +98,7 @@ config USBDEBUG_DIRECT It also requires a USB2 controller which supports the EHCI Debug Port capability. Controllers which are known to work: - + * 10b9:5239 ALi Corporation USB 2.0 (USB PCI card) * 8086:24cd Intel ICH4/ICH4-M * 8086:24dd Intel ICH5 diff --git a/src/console/btext_console.c b/src/console/btext_console.c index b1b10e63cb..56d893e36e 100644 --- a/src/console/btext_console.c +++ b/src/console/btext_console.c @@ -62,8 +62,8 @@ u32 boot_text_mapped; boot_infos_t disp_bi; -#define BTEXT -#define BTDATA +#define BTEXT +#define BTDATA /* This function will enable the early boot text when doing OF booting. This @@ -100,7 +100,7 @@ btext_setup_display(u32 width, u32 height, u32 depth, u32 pitch, * changes. */ -void +void map_boot_text(void) { #if 0 @@ -111,9 +111,9 @@ map_boot_text(void) return; base = ((unsigned long) bi->dispDeviceBase) & 0xFFFFF000UL; offset = ((unsigned long) bi->dispDeviceBase) - base; - size = bi->dispDeviceRowBytes * bi->dispDeviceRect[3] + offset + size = bi->dispDeviceRowBytes * bi->dispDeviceRect[3] + offset + bi->dispDeviceRect[0]; - bi->logicalDisplayBase = ioremap(base,0x800000 ); + bi->logicalDisplayBase = ioremap(base,0x800000 ); if (bi->logicalDisplayBase == 0) return; // bi->logicalDisplayBase += offset; @@ -360,7 +360,7 @@ static u32 expand_bits_8[16] BTDATA = { 0x0000ffff,0xff00ffff,0x00ffffff,0xffffffff #else #error FIXME: No endianness?? -#endif +#endif }; #if 0 static const u32 expand_bits_16[4] BTDATA = { diff --git a/src/console/console.c b/src/console/console.c index 327ad19017..016c3b9664 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -1,5 +1,5 @@ /* - * Bootstrap code for the INTEL + * Bootstrap code for the INTEL */ #include @@ -18,7 +18,7 @@ void console_init(void) struct console_driver *driver; if(get_option(&console_loglevel, "debug_level")) console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; - + for(driver = console_drivers; driver < econsole_drivers; driver++) { if (!driver->init) continue; @@ -38,7 +38,7 @@ void console_tx_flush(void) { struct console_driver *driver; for(driver = console_drivers; driver < econsole_drivers; driver++) { - if (!driver->tx_flush) + if (!driver->tx_flush) continue; driver->tx_flush(); } @@ -99,7 +99,7 @@ void __attribute__((noreturn)) die(const char *msg) void console_init(void) { - static const char console_test[] = + static const char console_test[] = "\n\ncoreboot-" COREBOOT_VERSION COREBOOT_EXTRA_VERSION diff --git a/src/console/logbuf_console.c b/src/console/logbuf_console.c index 3b6c744503..a76791d542 100644 --- a/src/console/logbuf_console.c +++ b/src/console/logbuf_console.c @@ -2,7 +2,7 @@ #define LOGBUF_SIZE 1024 -// KEEP THIS GLOBAL. +// KEEP THIS GLOBAL. // I need the address so I can watch it with the ARIUM hardware. RGM. char logbuf[LOGBUF_SIZE]; int logbuf_offset = 0; diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index fd71ff7dc2..20deaa72e3 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -38,17 +38,17 @@ static void ttyS0_init(void) uart8250_init(CONFIG_TTYS0_BASE, divisor, CONFIG_TTYS0_LCS); } -static void ttyS0_tx_byte(unsigned char data) +static void ttyS0_tx_byte(unsigned char data) { uart8250_tx_byte(CONFIG_TTYS0_BASE, data); } -static unsigned char ttyS0_rx_byte(void) +static unsigned char ttyS0_rx_byte(void) { return uart8250_rx_byte(CONFIG_TTYS0_BASE); } -static int ttyS0_tst_byte(void) +static int ttyS0_tst_byte(void) { return uart8250_can_rx_byte(CONFIG_TTYS0_BASE); } diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 7407c420ab..4a745233b9 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 3c75e3d704..944fd5b96f 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -30,7 +30,7 @@ static int skip_atoi(const char **s) #define SPECIAL 32 /* 0x */ #define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ -static int number(void (*tx_byte)(unsigned char byte), +static int number(void (*tx_byte)(unsigned char byte), unsigned long long num, int base, int size, int precision, int type) { char c,sign,tmp[66]; @@ -112,7 +112,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args int precision; /* min. # of digits for integers; max number of chars for from string */ int qualifier; /* 'h', 'l', or 'L' for integer fields */ - + int count; for (count=0; *fmt ; ++fmt) { @@ -120,7 +120,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args tx_byte(*fmt), count++; continue; } - + /* process flags */ flags = 0; repeat: @@ -132,7 +132,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args case '#': flags |= SPECIAL; goto repeat; case '0': flags |= ZEROPAD; goto repeat; } - + /* get field width */ field_width = -1; if (is_digit(*fmt)) @@ -150,7 +150,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args /* get the precision */ precision = -1; if (*fmt == '.') { - ++fmt; + ++fmt; if (is_digit(*fmt)) precision = skip_atoi(&fmt); else if (*fmt == '*') { diff --git a/src/cpu/amd/dualcore/Makefile.inc b/src/cpu/amd/dualcore/Makefile.inc index ee2d93c928..8b6d688300 100644 --- a/src/cpu/amd/dualcore/Makefile.inc +++ b/src/cpu/amd/dualcore/Makefile.inc @@ -1,2 +1,2 @@ -# This is a leaf Makefile, no conditionals. If it is included it will be used. +# This is a leaf Makefile, no conditionals. If it is included it will be used. obj-y += amd_sibling.o diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index 28a813c6a5..af96265d6c 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -27,12 +27,12 @@ static int get_max_siblings(int nodes) for(nodeid=0; nodeid> 12) & 3; + j = (pci_read_config32(dev, 0xe8) >> 12) & 3; if(siblings < j) { siblings = j; } } - + return siblings; } @@ -47,7 +47,7 @@ static void enable_apic_ext_id(int nodes) dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); val = pci_read_config32(dev, 0x68); val |= (1<<17)|(1<<18); - pci_write_config32(dev, 0x68, val); + pci_write_config32(dev, 0x68, val); } } @@ -70,9 +70,9 @@ unsigned get_apicid_base(unsigned ioapic_num) siblings = get_max_siblings(nodes); if(bsp_apic_id > 0) { // io apic could start from 0 - return 0; + return 0; } else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0 - return 1; + return 1; } nb_cfg_54 = read_nb_cfg_54(); @@ -100,7 +100,7 @@ unsigned get_apicid_base(unsigned ioapic_num) //4:10 for two way 8:12 for four way 16:16 for eight way //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency? - apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes; + apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes; } else { @@ -112,7 +112,7 @@ unsigned get_apicid_base(unsigned ioapic_num) printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n"); enable_apic_ext_id(nodes); } - + return apicid_base; } @@ -145,7 +145,7 @@ void amd_sibling_init(device_t cpu) siblings); #endif - nb_cfg_54 = read_nb_cfg_54(); + nb_cfg_54 = read_nb_cfg_54(); #if 1 id = get_node_core_id(nb_cfg_54); // pre e0 nb_cfg_54 can not be set @@ -159,7 +159,7 @@ void amd_sibling_init(device_t cpu) return; } #endif - + /* I am the primary cpu start up my siblings */ for(i = 1; i <= siblings; i++) { @@ -191,7 +191,7 @@ void amd_sibling_init(device_t cpu) new->path.apic.core_id = i; #if 1 - printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", + printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", cpu->path.apic.apic_id, new->path.apic.apic_id); #endif diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index a2b180b2b6..9a1a9c53d4 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -14,7 +14,7 @@ unsigned int read_nb_cfg_54(void) return ( ( msr.hi >> (54-32)) & 1); } -static inline unsigned get_initial_apicid(void) +static inline unsigned get_initial_apicid(void) { return ((cpuid_ebx(1) >> 24) & 0xf); } @@ -22,7 +22,7 @@ static inline unsigned get_initial_apicid(void) //called by amd_siblings too #define CORE_ID_BIT 1 #define NODE_ID_BIT 3 -struct node_core_id get_node_core_id(unsigned nb_cfg_54) +struct node_core_id get_node_core_id(unsigned nb_cfg_54) { struct node_core_id id; // get the apicid via cpuid(1) ebx[27:24] @@ -31,8 +31,8 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54) id.coreid = (cpuid_ebx(1) >> 24) & 0xf; id.nodeid = (id.coreid>>CORE_ID_BIT); id.coreid &= ((1<> 24) & 0xf; diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index d0beb04c98..db3debce2e 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -1,4 +1,4 @@ -# no conditionals here. If you include this file from a socket, then you get all the binaries. +# no conditionals here. If you include this file from a socket, then you get all the binaries. driver-y += model_10xxx_init.o obj-y += update_microcode.o obj-y += apic_timer.o diff --git a/src/cpu/amd/model_10xxx/mc_patch_01000095.h b/src/cpu/amd/model_10xxx/mc_patch_01000095.h index 1227f310f1..bfb2e107f7 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_01000095.h +++ b/src/cpu/amd/model_10xxx/mc_patch_01000095.h @@ -112,7 +112,7 @@ 0x0f, 0xe0, 0xdf, 0xf0, 0x23, 0x03, 0x00, 0x8e, 0x03, 0xff, 0x00, 0xfe, 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80, - + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index 5a19547b4d..992c957913 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -134,12 +134,12 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x100f22 }, { X86_VENDOR_AMD, 0x100f23 }, { X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */ - { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */ - { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */ - { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */ - { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ - { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ - { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */ + { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */ + { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */ + { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ + { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ + { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ { 0, 0 }, }; diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc index ea3088b46a..d7490e8fa9 100644 --- a/src/cpu/amd/model_fxx/Makefile.inc +++ b/src/cpu/amd/model_fxx/Makefile.inc @@ -1,4 +1,4 @@ -# no conditionals here. If you include this file from a socket, then you get all the binaries. +# no conditionals here. If you include this file from a socket, then you get all the binaries. driver-y += model_fxx_init.o obj-y += apic_timer.o obj-y += model_fxx_update_microcode.o diff --git a/src/cpu/amd/model_fxx/apic_timer.c b/src/cpu/amd/model_fxx/apic_timer.c index 8eeb32fee9..6eb99a4eba 100644 --- a/src/cpu/amd/model_fxx/apic_timer.c +++ b/src/cpu/amd/model_fxx/apic_timer.c @@ -25,5 +25,5 @@ void udelay(unsigned usecs) do { value = lapic_read(LAPIC_TMCCT); } while((start - value) < ticks); - + } diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index edc7ac909c..bfbc93d577 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -424,7 +424,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) static u32 calc_common_fidvid(unsigned fidvid, unsigned fidvidx) { - /* FIXME: need to check the change path to verify if it is reachable + /* FIXME: need to check the change path to verify if it is reachable * when common fid is small than 1.6G */ if ((fidvid & 0xff00) <= (fidvidx & 0xff00)) { return fidvid; @@ -549,7 +549,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid) /* let all ap trains to state 1 */ lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 1); - /* calculate the common max fid/vid that could be used for + /* calculate the common max fid/vid that could be used for * all APs and BSP */ #if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 ap_apicidx.num = 0; diff --git a/src/cpu/amd/model_fxx/microcode_rev_c.h b/src/cpu/amd/model_fxx/microcode_rev_c.h index f102d37d0f..980572439f 100644 --- a/src/cpu/amd/model_fxx/microcode_rev_c.h +++ b/src/cpu/amd/model_fxx/microcode_rev_c.h @@ -95,7 +95,7 @@ 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80, /* 1088=64 * 17 0 */ -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/src/cpu/amd/model_fxx/microcode_rev_d.h b/src/cpu/amd/model_fxx/microcode_rev_d.h index 7fc0666de6..61a510c2b2 100644 --- a/src/cpu/amd/model_fxx/microcode_rev_d.h +++ b/src/cpu/amd/model_fxx/microcode_rev_d.h @@ -94,7 +94,7 @@ 0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe, 0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80, /* 1088=64 * 17 0 */ -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/src/cpu/amd/model_fxx/microcode_rev_e.h b/src/cpu/amd/model_fxx/microcode_rev_e.h index 8d9a5813d4..7cdeed0016 100644 --- a/src/cpu/amd/model_fxx/microcode_rev_e.h +++ b/src/cpu/amd/model_fxx/microcode_rev_e.h @@ -95,7 +95,7 @@ 0xfe, 0x01, 0xfc, 0x1b, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80, /* 1088=64 * 17 0 */ -0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index 68a2cea070..976168102b 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -94,7 +94,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { #endif #if CONFIG_K8_REV_F_SUPPORT == 1 - + #endif }; @@ -102,7 +102,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { unsigned new_id; int i; - + new_id = 0; for(i=0; i "AMD Opteron(tm) Processor 8100"? program_string[i]=(ModelNumber/10)+'0'; program_string[i+1]=(ModelNumber%10)+'0'; @@ -442,7 +442,7 @@ int init_processor_name(void) } } } - + printk(BIOS_DEBUG, "CPU model %s\n", program_string); for (i=0; i<6; i++) { diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c index 82570f5b0a..f900661959 100644 --- a/src/cpu/amd/model_gx2/cpubug.c +++ b/src/cpu/amd/model_gx2/cpubug.c @@ -50,8 +50,8 @@ pcideadlock(void) msr_t msr; /* - * forces serialization of all load misses. Setting this bit prevents the - * DM pipe from backing up if a read request has to be held up waiting + * forces serialization of all load misses. Setting this bit prevents the + * DM pipe from backing up if a read request has to be held up waiting * for PCI writes to complete. */ msr = rdmsr(CPU_DM_CONFIG0); @@ -61,14 +61,14 @@ pcideadlock(void) wrmsr(CPU_DM_CONFIG0, msr); /* interlock instruction fetches to WS regions with data accesses. - * This prevents an instruction fetch from going out to PCI if the + * This prevents an instruction fetch from going out to PCI if the * data side is about to make a request. */ msr = rdmsr(CPU_IM_CONFIG); msr.lo |= IM_CONFIG_LOWER_QWT_SET; wrmsr(CPU_IM_CONFIG, msr); - - /* write serialize memory hole to PCI. Need to unWS when something is + + /* write serialize memory hole to PCI. Need to unWS when something is * shadowed regardless of cachablility. */ msr.lo = 0x021212121; @@ -78,7 +78,7 @@ pcideadlock(void) wrmsr( CPU_RCONF_E0_FF, msr); } -/**************************************************************************** +/**************************************************************************** * * CPUbug784 * @@ -176,7 +176,7 @@ eng2900(void) wrmsr(0x3003, msr); /* change this value to zero if you need to disable this BTB SWAPSiF. */ - if (1) { + if (1) { /* Disable enable_actions in DIAGCTL while setting up GLCP */ msr.hi = 0; @@ -192,16 +192,16 @@ eng2900(void) msr.lo = 2; wrmsr(MSR_GLCP + 0x0016, msr); - /* The code below sets up the CPU to stall for 4 GeodeLink - * clocks when CPU is snooped. Because setting XSTATE to 0 - * overrides any other XSTATE action, the code will always - * stall for 4 GeodeLink clocks after a snoop request goes - * away even if it occured a clock or two later than a - * different snoop; the stall signal will never 'glitch high' + /* The code below sets up the CPU to stall for 4 GeodeLink + * clocks when CPU is snooped. Because setting XSTATE to 0 + * overrides any other XSTATE action, the code will always + * stall for 4 GeodeLink clocks after a snoop request goes + * away even if it occured a clock or two later than a + * different snoop; the stall signal will never 'glitch high' * for only one or two CPU clocks with this code. */ - /* Send mb0 port 3 requests to upper GeodeLink diag bits + /* Send mb0 port 3 requests to upper GeodeLink diag bits [63:32] */ msr.hi = 0; msr.lo = 0x80338041; @@ -222,25 +222,25 @@ eng2900(void) msr.lo = 0; wrmsr(MSR_GLCP + 0x004D, msr); - /* Writing action number 13: XSTATE=0 to occur when CPU is + /* Writing action number 13: XSTATE=0 to occur when CPU is snooped unless we're stalled */ msr.hi = 0; msr.lo = 0x00400000; wrmsr(MSR_GLCP + 0x0075, msr); - /* Writing action number 11: inc XSTATE every GeodeLink clock + /* Writing action number 11: inc XSTATE every GeodeLink clock unless we're idle */ msr.hi = 0; msr.lo = 0x30000; wrmsr(MSR_GLCP + 0x0073, msr); - /* Writing action number 5: STALL_CPU_PIPE when exitting idle + /* Writing action number 5: STALL_CPU_PIPE when exitting idle state or not in idle state */ msr.hi = 0; msr.lo = 0x00430000; wrmsr(MSR_GLCP + 0x006D, msr); - /* Writing DIAGCTL Register to enable the stall action and to + /* Writing DIAGCTL Register to enable the stall action and to let set5m watch the upper GeodeLink diag bits. */ msr.hi = 0; msr.lo = 0x80004000; @@ -338,7 +338,7 @@ static void bug118339(void) /***/ /****************************************************************************/ static void disablememoryreadorder(void) -{ +{ msr_t msr; msr = rdmsr(MC_CF8F_DATA); @@ -365,7 +365,7 @@ cpubug(void) case 0x20: pcideadlock(); eng1398(); - /* cs 5530 bug; ignore + /* cs 5530 bug; ignore bug752(); */ break; @@ -376,7 +376,7 @@ cpubug(void) bug118339(); break; case 0x22: - case 0x30: + case 0x30: break; default: printk(BIOS_ERR, "unknown rev %x, bailing\n", rev); diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c index 5e786910c5..3cb3cf1a58 100644 --- a/src/cpu/amd/model_gx2/cpureginit.c +++ b/src/cpu/amd/model_gx2/cpureginit.c @@ -18,7 +18,7 @@ BIST(void){ msr = rdmsr(msrnum); msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET; wrmsr(msrnum, msr); - + msr.lo = 0x00000003F; msr.hi = 0x000000000; msrnum = CPU_DM_BIST; @@ -29,7 +29,7 @@ BIST(void){ msr.lo &= 0x0F3FF0000; if (msr.lo != 0xfeff0000) goto BISTFail; - + msrnum = CPU_DM_CONFIG0; msr = rdmsr(msrnum); msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET; @@ -89,58 +89,58 @@ cpuRegInit (void){ msr.hi = 0; msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET; wrmsr(msrnum, msr); - + /* Set up GLCP to grab BTM data.*/ msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/ msr.hi = 0x0; msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/ wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/ - + /* ;Turn off debug clock*/ msrnum = 0x04C000016; /* DBG_CLK_CTL*/ msr.lo = 0x00; /* No clock*/ msr.hi = 0x00; wrmsr(msrnum, msr); - + /* ;Set debug clock to CPU*/ msrnum = 0x04C000016; /* DBG_CLK_CTL*/ msr.lo = 0x01; /* CPU CLOCK*/ msr.hi = 0x00; wrmsr(msrnum, msr); - + /* ;Set fifo ctl to BTM bits wide*/ msrnum = 0x04C00005E; /* FIFO_CTL*/ msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/ wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/ /* Bit [19] sets it up in slow data mode.*/ - + /* ;enable fifo loading - BTM sizing will constrain*/ /* ; only valid BTM packets to load - this action should always be on*/ - + msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/ msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/ msr.hi = 0x000000000; /* */ wrmsr(msrnum, msr); - + /* ;start storing diag data in the fifo*/ msrnum = 0x04C00005F; /* DIAG CTL*/ msr.lo = 0x080000000; /* enable actions*/ msr.hi = 0x000000000; wrmsr(msrnum, msr); - + /* Set up delay on data lines, so that the hold time*/ /* is 1 ns.*/ msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/ msr.lo = 0x082b5ad68; msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/ wrmsr(msrnum, msr); - + /* Set up DF to output diag information on DF pins.*/ msrnum = DF_GLD_MSR_MASTER_CONF; msr.lo = 0x0220; msr.hi = 0; wrmsr(msrnum, msr); - + msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/ msr.hi = 0x0; msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/ @@ -237,7 +237,7 @@ cpuRegInit (void){ /* */ /* This code disables the data cache. Don't execute this * unless you're testing something. - */ + */ /* Allow NVRam to override DM Setup*/ /*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/ { @@ -249,7 +249,7 @@ cpuRegInit (void){ } /* This code disables the instruction cache. Don't execute * this unless you're testing something. - */ + */ /* Allow NVRam to override IM Setup*/ /*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/ { diff --git a/src/cpu/amd/model_lx/cpubug.c b/src/cpu/amd/model_lx/cpubug.c index 203d63b81e..e3b6e511ee 100644 --- a/src/cpu/amd/model_lx/cpubug.c +++ b/src/cpu/amd/model_lx/cpubug.c @@ -44,15 +44,15 @@ static void pcideadlock(void) msr_t msr; /* - * forces serialization of all load misses. Setting this bit prevents the - * DM pipe from backing up if a read request has to be held up waiting + * forces serialization of all load misses. Setting this bit prevents the + * DM pipe from backing up if a read request has to be held up waiting * for PCI writes to complete. */ msr = rdmsr(CPU_DM_CONFIG0); msr.lo |= DM_CONFIG0_LOWER_MISSER_SET; wrmsr(CPU_DM_CONFIG0, msr); - /* write serialize memory hole to PCI. Need to unWS when something is + /* write serialize memory hole to PCI. Need to unWS when something is * shadowed regardless of cachablility. */ msr.lo = 0x021212121; diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c index 492ee8fac0..62fa973a8c 100644 --- a/src/cpu/amd/model_lx/cpureginit.c +++ b/src/cpu/amd/model_lx/cpureginit.c @@ -248,8 +248,8 @@ void cpuRegInit(void) msr.hi |= ARB_UPPER_QUACK_EN_SET; wrmsr(msrnum, msr); - /* GLIU port active enable, limit south pole masters - * (AES and PCI) to one outstanding transaction. + /* GLIU port active enable, limit south pole masters + * (AES and PCI) to one outstanding transaction. */ print_debug(" GLIU port active enable\n"); msrnum = GLIU1_PORT_ACTIVE; diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c index c7b45470e6..53c0a851dc 100644 --- a/src/cpu/amd/model_lx/msrinit.c +++ b/src/cpu/amd/model_lx/msrinit.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify @@ -24,7 +24,7 @@ struct msrinit { msr_t msr; }; -static const struct msrinit msr_table[] = +static const struct msrinit msr_table[] = { {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB. * Rom Properties: Write Serialize, WriteProtect. @@ -35,7 +35,7 @@ static const struct msrinit msr_table[] = {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */ {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */ {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */ - + /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */ {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index d5e8338cad..c113f3f8fa 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -5,7 +5,7 @@ #include #include -static unsigned long resk(uint64_t value) +static unsigned long resk(uint64_t value) { unsigned long resultk; if (value < (1ULL << 42)) { @@ -98,7 +98,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n", start_mtrr, last_mtrr); set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM); - + } void amd_setup_mtrrs(void) @@ -118,7 +118,7 @@ void amd_setup_mtrrs(void) printk(BIOS_DEBUG, "\n"); /* Initialized the fixed_mtrrs to uncached */ - printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n", + printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n", 0, NUM_FIXED_RANGES); set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE); @@ -162,7 +162,7 @@ void amd_setup_mtrrs(void) wrmsr(i, msr); } - /* Enable Variable Mtrrs + /* Enable Variable Mtrrs * Enable the RdMem and WrMem bits in the fixed mtrrs. * Disable access to the RdMem and WrMem in the fixed mtrr. */ diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c index c56117485a..e6232a8eb4 100644 --- a/src/cpu/amd/sc520/raminit.c +++ b/src/cpu/amd/sc520/raminit.c @@ -65,13 +65,13 @@ void setupsc520(void) /* do this to see if MMCR will start acting right. we suspect * you have to do SOMETHING to get things going. I'm really - * starting to hate this processor. + * starting to hate this processor. */ - - /* no, that did not help. I wonder what will? + + /* no, that did not help. I wonder what will? * outl(0x800df0cb, 0xfffc); */ - + /* well, this is special! You have to do SHORT writes to the * locations, even though they are CHAR in size and CHAR aligned * and technically, a SHORT write will result in -- yoo ha! -- @@ -80,7 +80,7 @@ void setupsc520(void) * it now reliably comes up after power cycle with printk. Ah yi * yi. */ - + /* turn off the write buffer*/ /* per the note above, make this a short? Let's try it. */ sp = (unsigned short *)0xfffef040; @@ -92,7 +92,7 @@ void setupsc520(void) /* moved to romstage.c by Stepan, Ron says: */ /* NOTE: move this to mainboard.c ASAP */ setup_pars(); - + /* CPCSF register */ sp = (unsigned short *)0xfffefc24; *sp = 0xfe; @@ -120,7 +120,7 @@ void setupsc520(void) /*set the GP RD offset */ sp = (unsigned short *)0xfffefc0c; *sp = 0x00001; - /*set the GP WR pulse width*/ + /*set the GP WR pulse width*/ sp = (unsigned short *)0xfffefc0d; *sp = 0x00003; /*set the GP WR offset*/ @@ -164,19 +164,19 @@ void setupsc520(void) /*; set the interrupt mapping registers.*/ cp = (unsigned char *)0x0fffefd20; *cp = 0x01; - + cp = (unsigned char *)0x0fffefd28; *cp = 0x0c; - + cp = (unsigned char *)0x0fffefd29; *cp = 0x0b; - + cp = (unsigned char *)0x0fffefd30; *cp = 0x07; - + cp = (unsigned char *)0x0fffefd43; *cp = 0x03; - + cp = (unsigned char *)0x0fffefd51; *cp = 0x02; #endif @@ -186,8 +186,8 @@ void setupsc520(void) outl(0x08000683c, 0xcf8); outl(0xc, 0xcfc); /* set the interrupt line */ - - /* Set the SC520 PCI host bridge to target mode to + + /* Set the SC520 PCI host bridge to target mode to * allow external bus mastering events */ /* index the status command register on device 0*/ @@ -195,7 +195,7 @@ void setupsc520(void) outl(0x2, 0xcfc); /*set the memory access enable bit*/ OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */ } - + /* * @@ -228,7 +228,7 @@ void setupsc520(void) #define ROW11_DATA 0x07070707 /* 11 row data/also bank switch (MASK)*/ #define ROW10_DATA 0xaaaaaaaa /* 10 row data/also bank switch (MASK)*/ -void +void dummy_write(void){ volatile unsigned short *ptr = (volatile unsigned short *)CACHELINESZ; *ptr = 0; @@ -247,16 +247,16 @@ static void dumpram(void){ print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\n"); } -/* there is a lot of silliness in the amd code, and it is - * causing romcc real headaches, so we're going to be be a little +/* there is a lot of silliness in the amd code, and it is + * causing romcc real headaches, so we're going to be be a little * less silly. - * so, the order of ops is: + * so, the order of ops is: * for i in 3 to 0 - * see if bank is there. + * see if bank is there. * if we can write a word, and read it back, to hell with paranoia - * the bank is there. So write the magic byte, read it back, and - * use that to get size, etc. Try to keep things very simple, - * so people can actually follow the damned code. + * the bank is there. So write the magic byte, read it back, and + * use that to get size, etc. Try to keep things very simple, + * so people can actually follow the damned code. */ /* cache is assumed to be disabled */ @@ -273,14 +273,14 @@ int sizemem(void) /* no ecc interrupts of any kind. */ *eccctl = 0; /* Set SDRAM timing for slowest speed. */ - *drcmctl = 0x1e; + *drcmctl = 0x1e; /* setup dram register for all banks * with max cols and max banks * this is the oldest trick in the book. You are going to set up for max rows - * and cols, then do a write, then see if the data is wrapped to low memory. - * you can actually tell by which data gets to which low memory, - * exactly how many rows and cols you have. + * and cols, then do a write, then see if the data is wrapped to low memory. + * you can actually tell by which data gets to which low memory, + * exactly how many rows and cols you have. */ *drccfg=0xbbbb; @@ -339,24 +339,24 @@ int sizemem(void) *lp = 0xdeadbeef; print_err("assigned l ... \n"); if (*lp != 0xdeadbeef) { - print_err(" no memory at bank "); - // print_err_hex8(bank); + print_err(" no memory at bank "); + // print_err_hex8(bank); // print_err(" value "); print_err_hex32(*lp); - print_err("\n"); + print_err("\n"); // continue; } *drcctl = 2; dummy_write(); *drccfg = *drccfg >> 4; l = *drcbendadr; - l >>= 8; + l >>= 8; *drcbendadr = l; print_err("loop around\n"); *drcctl = 0; dummy_write(); } #if 0 - /* enable last bank and setup ending address + /* enable last bank and setup ending address * register for max ram in last bank */ *drcbendadr=0x0ff000000; @@ -410,10 +410,10 @@ int sizemem(void) bank = 3; - /* this is really ugly, it is right from assembly code. + /* this is really ugly, it is right from assembly code. * we need to clean it up later */ - + start: /* write col 11 wrap adr */ COL11_ADR=COL11_DATA; @@ -519,7 +519,7 @@ print_err("4b\n"); print_err("cols"); print_err_hex32(cols); print_err("\n"); cols -= COL08_DATA; - /* cols now is in the range of 0 1 2 3 ... + /* cols now is in the range of 0 1 2 3 ... */ i = cols&3; // i = cols + rows; @@ -533,22 +533,22 @@ print_err("4b\n"); /* what a fookin' mess this is */ if(banks==4) i+=8; /* <-- i holds merged value */ - /* i now has the col width in bits 0-1 and the bank count (2 or 4) + /* i now has the col width in bits 0-1 and the bank count (2 or 4) * in bit 3. - * this is the format for the drccfg register + * this is the format for the drccfg register */ - + /* fix ending addr mask*/ /*FIXME*/ /* let's just go with this to start ... see if we can get ANYWHERE */ /* need to get end addr. Need to do it with the bank in mind. */ /* - al = 3; + al = 3; al -= i&3; *drcbendaddr = rows >> al; - print_err("computed ending_adr = "); print_err_hex8(ending_adr); + print_err("computed ending_adr = "); print_err_hex8(ending_adr); print_err("\n"); - + */ bad_reinit: /* issue all banks recharge */ @@ -557,7 +557,7 @@ bad_reinit: /* update ending address register */ // *drcbendadr = ending_adr; - + /* update config register */ *drccfg &= ~(0xff << bank*4); if (ending_adr) @@ -579,11 +579,11 @@ bad_reinit: *drcctl=0x18; dummy_write(); return bank; - + bad_ram: print_info("bad ram!\n"); - /* you are here because the read-after-write failed, - * in most cases because: no ram in that bank! + /* you are here because the read-after-write failed, + * in most cases because: no ram in that bank! * set badbank to 1 and go to reinit */ ending_adr = 0; @@ -591,7 +591,7 @@ bad_ram: while(1) print_err("DONE NEXTBANK\n"); #endif -} +} /* note: based on AMD code*/ /* This code is known to work on the digital logic board and on the technologic @@ -600,7 +600,7 @@ bad_ram: int staticmem(void) { volatile unsigned long *zero = (unsigned long *) CACHELINESZ; - + /* set up 0x18 .. **/ *drcbendadr = 0x88; *drcmctl = 0x1e; @@ -609,7 +609,7 @@ int staticmem(void) *drcctl = 0x1; /* do the dummy write */ *zero = 0; - + /* precharge */ *drcctl = 2; *zero = 0; @@ -625,7 +625,7 @@ int staticmem(void) *drcctl = 3; *zero = 0; print_debug("DONE the load mode reg\n"); - + /* normal mode */ *drcctl = 0x0; *zero = 0; @@ -634,7 +634,7 @@ int staticmem(void) *zero = 0; print_debug("DONE the normal\n"); *zero = 0xdeadbeef; - if (*zero != 0xdeadbeef) + if (*zero != 0xdeadbeef) print_debug("NO LUCK\n"); else print_debug("did a store and load ...\n"); diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c index e867fae3d7..4c93ebd295 100644 --- a/src/cpu/amd/sc520/sc520.c +++ b/src/cpu/amd/sc520/sc520.c @@ -16,10 +16,10 @@ #include "chip.h" /* - * set up basic things ... - * PAR should NOT go here, as it might change with the mainboard. + * set up basic things ... + * PAR should NOT go here, as it might change with the mainboard. */ -static void cpu_init(device_t dev) +static void cpu_init(device_t dev) { unsigned long *l = (unsigned long *) 0xfffef088; int i; @@ -30,9 +30,9 @@ static void cpu_init(device_t dev) } -/* Ollie says: make a northbridge/amd/sc520. Ron sez: - * there is no real northbridge, keep it here in cpu. - * Ron wins, he's writing the code. +/* Ollie says: make a northbridge/amd/sc520. Ron sez: + * there is no real northbridge, keep it here in cpu. + * Ron wins, he's writing the code. */ static void sc520_enable_resources(struct device *dev) { unsigned char command; @@ -141,16 +141,16 @@ static void pci_domain_set_resources(device_t dev) for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { unsigned char reg; reg = pci_read_config8(mc_dev, ramregs[i]); - /* these are ENDING addresses, not sizes. + /* these are ENDING addresses, not sizes. * if there is memory in this slot, then reg will be > rambits. - * So we just take the max, that gives us total. + * So we just take the max, that gives us total. * We take the highest one to cover for once and future coreboot * bugs. We warn about bugs. */ if (reg > rambits) rambits = reg; if (reg < rambits) - printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", + printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", ramregs[i]); } printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); @@ -245,5 +245,5 @@ static void enable_dev(struct device *dev) struct chip_operations cpu_amd_sc520_ops = { CHIP_NAME("AMD Elan SC520 CPU") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 04c4d9ff58..870490c07d 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -1,5 +1,5 @@ # Note: From here on down, we are socket-centric. Socket choice determines -# what other cpu files are included. +# what other cpu files are included. # # Therefore: ONLY include Makefile.inc from socket directories! diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index f6a7e12e0d..41f3ce5b4d 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -305,11 +305,11 @@ lout: pushl %eax /* bist */ call main - /* + /* FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that. It is only needed if we want to go back */ - + /* We don't need cache as ram for now on */ /* disable cache */ movl %cr0, %eax @@ -396,7 +396,7 @@ lout: __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -404,7 +404,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 5e77a765a8..823d77c3a3 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -43,7 +43,7 @@ void intel_sibling_init(device_t cpu) } return; } - + /* I am the primary cpu start up my siblings */ for(i = 1; i < siblings; i++) { struct device_path cpu_path; @@ -61,7 +61,7 @@ void intel_sibling_init(device_t cpu) } #if 1 - printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", + printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", cpu->path.apic.apic_id, new->path.apic.apic_id); #endif @@ -72,6 +72,6 @@ void intel_sibling_init(device_t cpu) new->path.apic.apic_id); } } - + } diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 22c3a11503..93d2a687fb 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -59,7 +59,7 @@ void intel_update_microcode(const void *microcode_updates) const struct microcode *m; const char *c; msr_t msr; - + /* cpuid sets msr 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index fc20c6047f..8197898847 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -40,7 +40,7 @@ static const uint32_t microcode_updates[] = { 0x0, 0x0, 0x0, 0x0, }; -static inline void strcpy(char *dst, char *src) +static inline void strcpy(char *dst, char *src) { while (*src) *dst++ = *src++; } @@ -77,7 +77,7 @@ static void fill_processor_name(char *processor_name) /* Skip leading spaces */ processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') + while (*processor_name_start == ' ') processor_name_start++; memset(processor_name, 0, 49); @@ -197,7 +197,7 @@ static void configure_pic_thermal_sensors(void) #if CONFIG_USBDEBUG_DIRECT static unsigned ehci_debug_addr; #endif - + static void model_1067x_init(device_t cpu) { char processor_name[49]; @@ -214,7 +214,7 @@ static void model_1067x_init(device_t cpu) #if CONFIG_USBDEBUG_DIRECT // Is this caution really needed? - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 767c488d45..873c6e9479 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -1,18 +1,18 @@ -/* +/* * This file is part of the coreboot project. - * + * * Copyright (C) 2000,2007 Ronald G. Minnich * Copyright (C) 2007-2008 coresystems GmbH - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA @@ -206,7 +206,7 @@ clear_mtrrs: xorl %eax, %eax movl $((1024*1024) / 4), %ecx rep stosl - + post_code(0x37) #endif @@ -254,7 +254,7 @@ clear_mtrrs: __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -262,7 +262,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 143a6f473a..65dfebba5b 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -39,7 +39,7 @@ static const uint32_t microcode_updates[] = { 0x0, 0x0, 0x0, 0x0, }; -static inline void strcpy(char *dst, char *src) +static inline void strcpy(char *dst, char *src) { while (*src) *dst++ = *src++; } @@ -64,7 +64,7 @@ static void fill_processor_name(char *processor_name) /* Skip leading spaces */ processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') + while (*processor_name_start == ' ') processor_name_start++; memset(processor_name, 0, 49); @@ -175,7 +175,7 @@ static void model_106cx_init(device_t cpu) #if CONFIG_USBDEBUG_DIRECT // Is this caution really needed? - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index f2605ebd79..b6ea237366 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -26,7 +26,7 @@ static void model_69x_init(device_t dev) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index a921fbd368..783138ec83 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2010 Joseph Smith * @@ -44,7 +44,7 @@ static const uint32_t microcode_updates[] = { 0x0, 0x0, 0x0, 0x0, }; -static inline void strcpy(char *dst, char *src) +static inline void strcpy(char *dst, char *src) { while (*src) *dst++ = *src++; } @@ -69,7 +69,7 @@ static void fill_processor_name(char *processor_name) /* Skip leading spaces */ processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') + while (*processor_name_start == ' ') processor_name_start++; memset(processor_name, 0, 49); @@ -96,7 +96,7 @@ static void model_6bx_init(device_t cpu) #if CONFIG_USBDEBUG_DIRECT // Is this caution really needed? - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 936c67afc9..26c1b99499 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -26,7 +26,7 @@ static void model_6dx_init(device_t dev) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index d4f5d8bf5e..623b0a30a1 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -1,18 +1,18 @@ -/* +/* * This file is part of the coreboot project. - * + * * Copyright (C) 2000,2007 Ronald G. Minnich * Copyright (C) 2007-2008 coresystems GmbH - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA @@ -206,7 +206,7 @@ clear_mtrrs: xorl %eax, %eax movl $((1024*1024) / 4), %ecx rep stosl - + post_code(0x37) #endif @@ -254,7 +254,7 @@ clear_mtrrs: __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -262,7 +262,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index f879f34869..4f1d2043b6 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -44,7 +44,7 @@ static const uint32_t microcode_updates[] = { 0x0, 0x0, 0x0, 0x0, }; -static inline void strcpy(char *dst, char *src) +static inline void strcpy(char *dst, char *src) { while (*src) *dst++ = *src++; } @@ -69,7 +69,7 @@ static void fill_processor_name(char *processor_name) /* Skip leading spaces */ processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') + while (*processor_name_start == ' ') processor_name_start++; memset(processor_name, 0, 49); @@ -204,7 +204,7 @@ static void model_6ex_init(device_t cpu) #if CONFIG_USBDEBUG_DIRECT // Is this caution really needed? - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index f46e5bdc48..0717116d0a 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -1,18 +1,18 @@ -/* +/* * This file is part of the coreboot project. - * + * * Copyright (C) 2000,2007 Ronald G. Minnich * Copyright (C) 2007-2008 coresystems GmbH - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA @@ -213,7 +213,7 @@ clear_mtrrs: xorl %eax, %eax movl $((1024*1024) / 4), %ecx rep stosl - + post_code(0x37) #endif @@ -268,7 +268,7 @@ clear_mtrrs: __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -276,7 +276,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index f00aba8e33..3d1e9ba9a3 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -58,7 +58,7 @@ static const uint32_t microcode_updates[] = { 0x0, 0x0, 0x0, 0x0, }; -static inline void strcpy(char *dst, char *src) +static inline void strcpy(char *dst, char *src) { while (*src) *dst++ = *src++; } @@ -83,7 +83,7 @@ static void fill_processor_name(char *processor_name) /* Skip leading spaces */ processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') + while (*processor_name_start == ' ') processor_name_start++; memset(processor_name, 0, 49); @@ -214,7 +214,7 @@ static void configure_pic_thermal_sensors(void) #if CONFIG_USBDEBUG_DIRECT static unsigned ehci_debug_addr; #endif - + static void model_6fx_init(device_t cpu) { char processor_name[49]; @@ -231,7 +231,7 @@ static void model_6fx_init(device_t cpu) #if CONFIG_USBDEBUG_DIRECT // Is this caution really needed? - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif diff --git a/src/cpu/intel/model_6xx/microcode_MU16810d.h b/src/cpu/intel/model_6xx/microcode_MU16810d.h index ce207efa76..ef1ff7dd1d 100644 --- a/src/cpu/intel/model_6xx/microcode_MU16810d.h +++ b/src/cpu/intel/model_6xx/microcode_MU16810d.h @@ -1,12 +1,12 @@ /* - Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000. + Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000. - These microcode updates are distributed for the sole purpose of + These microcode updates are distributed for the sole purpose of installation in the BIOS or Operating System of computer systems which include an Intel P6 family microprocessor sold or distributed to or by you. You are authorized to copy and install this material on such systems. You are not authorized to use this material for - any other purpose. + any other purpose. */ /* MU16810d.inc */ diff --git a/src/cpu/intel/model_6xx/microcode_MU16830c.h b/src/cpu/intel/model_6xx/microcode_MU16830c.h index 2724e7bae4..602739c368 100644 --- a/src/cpu/intel/model_6xx/microcode_MU16830c.h +++ b/src/cpu/intel/model_6xx/microcode_MU16830c.h @@ -1,12 +1,12 @@ /* - Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000. + Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000. - These microcode updates are distributed for the sole purpose of + These microcode updates are distributed for the sole purpose of installation in the BIOS or Operating System of computer systems which include an Intel P6 family microprocessor sold or distributed to or by you. You are authorized to copy and install this material on such systems. You are not authorized to use this material for - any other purpose. + any other purpose. */ /* MU16830c.inc */ diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 7efdf2119e..6c795eab32 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -16,7 +16,7 @@ static uint32_t microcode_updates[] = { * microcode update lengths. They are encoded in int 8 and 9. A * dummy header of nulls must terminate the list. */ -#include "microcode_MU16810d.h" +#include "microcode_MU16810d.h" #include "microcode_MU16830c.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, @@ -32,7 +32,7 @@ static void model_6xx_init(device_t dev) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index c4d1ef085e..568d4d70ee 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = { * microcode update lengths. They are encoded in int 8 and 9. A * dummy header of nulls must terminate the list. */ - + /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -32,7 +32,7 @@ static void model_f0x_init(device_t dev) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_f0x/multiplier.h b/src/cpu/intel/model_f0x/multiplier.h index e2f81362e8..a3b1fcb309 100644 --- a/src/cpu/intel/model_f0x/multiplier.h +++ b/src/cpu/intel/model_f0x/multiplier.h @@ -1,5 +1,5 @@ -/* +/* ** NMI A20M IGNNE INTR * X8 H H H H * X9 H H H L projected @@ -8,7 +8,7 @@ * X12 H L H H * X13 H L H L * X14 H L L H - * X15 H L L L + * X15 H L L L * X16 L H H H * X17 L H H L * X18 L H L H @@ -18,7 +18,7 @@ * X22 L L L H projected * X23 L L L L projected * - ** NMI INTR IGNNE A20M + ** NMI INTR IGNNE A20M * X8 H H H H * X9 H L H H projected * X10 H H L H @@ -26,7 +26,7 @@ * X12 H H H L * X13 H L H L * X14 H H L L - * X15 H L L L + * X15 H L L L * X16 L H H H * X17 L L H H * X18 L H L H diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index a3a66783c4..f8dd1d85f7 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = { * microcode update lengths. They are encoded in int 8 and 9. A * dummy header of nulls must terminate the list. */ - + /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @@ -32,7 +32,7 @@ static void model_f1x_init(device_t dev) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_f1x/multiplier.h b/src/cpu/intel/model_f1x/multiplier.h index e2f81362e8..a3b1fcb309 100644 --- a/src/cpu/intel/model_f1x/multiplier.h +++ b/src/cpu/intel/model_f1x/multiplier.h @@ -1,5 +1,5 @@ -/* +/* ** NMI A20M IGNNE INTR * X8 H H H H * X9 H H H L projected @@ -8,7 +8,7 @@ * X12 H L H H * X13 H L H L * X14 H L L H - * X15 H L L L + * X15 H L L L * X16 L H H H * X17 L H H L * X18 L H L H @@ -18,7 +18,7 @@ * X22 L L L H projected * X23 L L L L projected * - ** NMI INTR IGNNE A20M + ** NMI INTR IGNNE A20M * X8 H H H H * X9 H L H H projected * X10 H H L H @@ -26,7 +26,7 @@ * X12 H H H L * X13 H L H L * X14 H H L L - * X15 H L L L + * X15 H L L L * X16 L H H H * X17 L L H H * X18 L H L H diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index d7b77efb72..9c7af78969 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -37,7 +37,7 @@ static void model_f2x_init(device_t cpu) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_f3x/microcode_M1DF340E.h b/src/cpu/intel/model_f3x/microcode_M1DF340E.h index a378fba8ac..55854b583a 100644 --- a/src/cpu/intel/model_f3x/microcode_M1DF340E.h +++ b/src/cpu/intel/model_f3x/microcode_M1DF340E.h @@ -9,7 +9,7 @@ */ /* M1DF340E.TXT - Noconoa D-0 */ - + 0x00000001, /* Header Version */ 0x0000000e, /* Patch ID */ diff --git a/src/cpu/intel/model_f3x/microcode_M1DF3413.h b/src/cpu/intel/model_f3x/microcode_M1DF3413.h index f2a0a8f79d..676d67c061 100644 --- a/src/cpu/intel/model_f3x/microcode_M1DF3413.h +++ b/src/cpu/intel/model_f3x/microcode_M1DF3413.h @@ -2,7 +2,7 @@ * microcode update lengths. They are encoded in int 8 and 9. A * dummy header of nulls must terminate the list. */ - + /* Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000. These microcode updates are distributed for the sole purpose of @@ -12,9 +12,9 @@ on such systems. You are not authorized to use this material for any other purpose. */ - + /* M1DF3413.TXT - Noconoa D-0 */ - + 0x00000001, /* Header Version */ 0x00000013, /* Patch ID */ 0x07302004, /* DATE */ @@ -27,7 +27,7 @@ 0x00000000, /* reserved */ 0x00000000, /* reserved */ 0x00000000, /* reserved */ - + 0x9fbf327a, 0x2b41b451, 0xb2abaca8, diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index cbdd50ac2f..68b22c99a8 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = { * microcode update lengths. They are encoded in int 8 and 9. A * dummy header of nulls must terminate the list. */ - + #include "microcode_M1DF3413.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, @@ -33,7 +33,7 @@ static void model_f3x_init(device_t cpu) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index a48c7592ba..d6acddee09 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -17,7 +17,7 @@ static uint32_t microcode_updates[] = { * microcode update lengths. They are encoded in int 8 and 9. A * dummy header of nulls must terminate the list. */ - + #include "microcode_MBDF410D.h" /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, @@ -33,7 +33,7 @@ static void model_f4x_init(device_t cpu) x86_enable_cache(); x86_setup_mtrrs(36); x86_mtrr_check(); - + /* Update the microcode */ intel_update_microcode(microcode_updates); diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index faa74d3390..2fc27cff78 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -8,7 +8,7 @@ config CPU_INTEL_SOCKET_MPGA604 select UDELAY_TSC # mPGA604 are usually Intel Netburst CPUs which should have SSE2 -# but the ramtest.c code on the Dell S1850 seems to choke on +# but the ramtest.c code on the Dell S1850 seems to choke on # enabling it, so disable it for now. config SSE2 bool diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 920984369e..33898e3280 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 8a12c8fa48..8bc274b381 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -179,12 +179,12 @@ testok: movb $0x40,%al pushl %eax /* bist */ call main - /* + /* * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we * get STACK up, we restore that. It is only needed if we * want to go back. */ - + /* We don't need cache as ram for now on */ /* disable cache */ movl %cr0, %eax @@ -207,7 +207,7 @@ testok: movb $0x40,%al movl $(0 | 6), %eax //movl $(0 | MTRR_TYPE_WRBACK), %eax wrmsr - + /* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff; * If 1M cacheable, then when S3 resume, there is stange color on * screen for 2 sec. suppose problem of a0000-dfffff and cache. @@ -218,7 +218,7 @@ testok: movb $0x40,%al movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax wrmsr - + movl $0x202, %ecx xorl %edx, %edx movl $(0x80000 | 6), %eax @@ -229,7 +229,7 @@ testok: movb $0x40,%al movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax wrmsr - + movl $0x204, %ecx xorl %edx, %edx movl $(0xc0000 | 6), %eax @@ -239,8 +239,8 @@ testok: movb $0x40,%al movl $0x205, %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax - wrmsr - + wrmsr + /* cache XIP_ROM_BASE-SIZE to speedup coreboot code */ movl $0x206, %ecx xorl %edx, %edx @@ -267,7 +267,7 @@ testok: movb $0x40,%al __main: post_code(0x11) cld /* clear direction flag */ - + movl %ebp, %esi movl $ROMSTAGE_STACK, %esp @@ -275,7 +275,7 @@ __main: pushl %esi call copy_and_run -.Lhlt: +.Lhlt: post_code(0xee) hlt jmp .Lhlt diff --git a/src/cpu/via/model_c3/model_c3_init.c b/src/cpu/via/model_c3/model_c3_init.c index ef979198da..291e4afef9 100644 --- a/src/cpu/via/model_c3/model_c3_init.c +++ b/src/cpu/via/model_c3/model_c3_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or diff --git a/src/cpu/via/model_c7/model_c7_init.c b/src/cpu/via/model_c7/model_c7_init.c index da946957c2..5474b8d6c7 100644 --- a/src/cpu/via/model_c7/model_c7_init.c +++ b/src/cpu/via/model_c7/model_c7_init.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -36,7 +36,7 @@ #define MSR_IA32_MISC_ENABLE 0x000001a0 static int c7a_speed_translation[] = { -// LFM HFM +// LFM HFM 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V @@ -51,7 +51,7 @@ static int c7a_speed_translation[] = { }; static int c7d_speed_translation[] = { -// LFM HFM +// LFM HFM 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M 0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V 0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 674315fbd2..1eb92c82d1 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -21,8 +21,8 @@ it with the version available from LANL. */ -/** Start code to put an i386 or later processor into 32-bit - * protected mode. +/** Start code to put an i386 or later processor into 32-bit + * protected mode. */ /* .section ".rom.text" */ @@ -31,7 +31,7 @@ it with the version available from LANL. .globl _start .type _start, @function -_start: +_start: cli /* Save the BIST result */ movl %eax, %ebp @@ -68,13 +68,13 @@ _start: * pratical problem of being able to write code that can * be relocated. * - * An lgdt call before we have memory enabled cannot be + * An lgdt call before we have memory enabled cannot be * position independent, as we cannot execute a call * instruction to get our current instruction pointer. * So while this code is relocateable it isn't arbitrarily * relocatable. * - * The criteria for relocation have been relaxed to their + * The criteria for relocation have been relaxed to their * utmost, so that we can use the same code for both * our initial entry point and startup of the second cpu. * The code assumes when executing at _start that: diff --git a/src/cpu/x86/16bit/reset16.lds b/src/cpu/x86/16bit/reset16.lds index 929740bd4c..cec03d6bc6 100644 --- a/src/cpu/x86/16bit/reset16.lds +++ b/src/cpu/x86/16bit/reset16.lds @@ -12,5 +12,5 @@ SECTIONS { *(.reset) . = 15 ; BYTE(0x00); - } + } } diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index bc5e4436ae..4e0f3b953a 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -18,23 +18,23 @@ gdtptr: .word 0 /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ /* selgdt 0x10,flat data segment */ - .word 0xffff, 0x0000 + .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 gdt_end: - + /* - * When we come here we are in protected mode. We expand + * When we come here we are in protected mode. We expand * the stack and copies the data segment from ROM to the * memory. * * After that, we call the chipset bootstrap routine that - * does what is left of the chipset initialization. + * does what is left of the chipset initialization. * * NOTE aligned to 4 so that we are sure that the prefetch * cache will be reloaded. @@ -45,7 +45,7 @@ protected_start: lgdt %cs:gdtptr ljmp $ROM_CODE_SEG, $__protected_start - + __protected_start: /* Save the BIST value */ movl %eax, %ebp diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 555d74eecc..c8f83b0dd0 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -5,11 +5,11 @@ void setup_lapic(void) { - /* this is so interrupts work. This is very limited scope -- + /* this is so interrupts work. This is very limited scope -- * linux will do better later, we hope ... */ - /* this is the first way we learned to do it. It fails on real SMP - * stuff. So we have to do things differently ... + /* this is the first way we learned to do it. It fails on real SMP + * stuff. So we have to do things differently ... * see the Intel mp1.4 spec, page A-3 */ @@ -33,25 +33,25 @@ void setup_lapic(void) lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK); /* Put the local apic in virtual wire mode */ - lapic_write_around(LAPIC_SPIV, + lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) & ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE); - lapic_write_around(LAPIC_LVT0, - (lapic_read_around(LAPIC_LVT0) & - ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | - LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | + lapic_write_around(LAPIC_LVT0, + (lapic_read_around(LAPIC_LVT0) & + ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | + LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | LAPIC_SEND_PENDING |LAPIC_LVT_RESERVED_1 | LAPIC_DELIVERY_MODE_MASK)) - | (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING | + | (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING | LAPIC_DELIVERY_MODE_EXTINT) ); - lapic_write_around(LAPIC_LVT1, - (lapic_read_around(LAPIC_LVT1) & - ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | - LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | + lapic_write_around(LAPIC_LVT1, + (lapic_read_around(LAPIC_LVT1) & + ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | + LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | LAPIC_SEND_PENDING |LAPIC_LVT_RESERVED_1 | LAPIC_DELIVERY_MODE_MASK)) - | (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING | + | (LAPIC_LVT_REMOTE_IRR |LAPIC_SEND_PENDING | LAPIC_DELIVERY_MODE_NMI) ); diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index dafc9a561c..5c1e7607e8 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -26,7 +26,7 @@ _secondary_start: movl %eax, %cr0 ljmpl $0x10, $1f -1: +1: .code32 movw $0x18, %ax movw %ax, %ds diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index d97cd93deb..1cbc544350 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -89,13 +89,13 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif - /* Set the default memory type and enable fixed and variable MTRRs + /* Set the default memory type and enable fixed and variable MTRRs */ /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; wrmsr(MTRRdefType_MSR, msr); - + } static inline void early_mtrr_init(void) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 94d7ca7d35..d44687a0e9 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -68,7 +68,7 @@ static void enable_var_mtrr(void) /* setting variable mtrr, comes from linux kernel source */ static void set_var_mtrr( - unsigned int reg, unsigned long basek, unsigned long sizek, + unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type, unsigned address_bits) { msr_t base, mask; @@ -81,7 +81,7 @@ static void set_var_mtrr( // do this. if (sizek == 0) { disable_cache(); - + msr_t zero; zero.lo = zero.hi = 0; /* The invalid bit is kept in the mask, so we simply clear the @@ -109,8 +109,8 @@ static void set_var_mtrr( mask.lo = 0; } - // it is recommended that we disable and enable cache when we - // do this. + // it is recommended that we disable and enable cache when we + // do this. disable_cache(); /* Bit 32-35 of MTRRphysMask should be set to 1 */ @@ -228,7 +228,7 @@ static unsigned fixed_mtrr_index(unsigned long addrk) return index; } -static unsigned int range_to_mtrr(unsigned int reg, +static unsigned int range_to_mtrr(unsigned int reg, unsigned long range_startk, unsigned long range_sizek, unsigned long next_range_startk, unsigned char type, unsigned address_bits) { @@ -253,7 +253,7 @@ static unsigned int range_to_mtrr(unsigned int reg, unsigned long sizek; /* Compute the maximum size I can make a range */ max_align = fls(range_startk); - align = fms(range_sizek); + align = fms(range_sizek); if (align > max_align) { align = max_align; } @@ -274,7 +274,7 @@ static unsigned int range_to_mtrr(unsigned int reg, return reg; } -static unsigned long resk(uint64_t value) +static unsigned long resk(uint64_t value) { unsigned long resultk; if (value < (1ULL << 42)) { @@ -298,7 +298,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n", start_mtrr, last_mtrr); set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK); - + } #ifndef CONFIG_VAR_MTRR_HOLE @@ -343,10 +343,10 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) return; } #endif - state->reg = range_to_mtrr(state->reg, state->range_startk, + state->reg = range_to_mtrr(state->reg, state->range_startk, state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits); #if CONFIG_VAR_MTRR_HOLE - state->reg = range_to_mtrr(state->reg, state->hole_startk, + state->reg = range_to_mtrr(state->reg, state->hole_startk, state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, state->address_bits); #endif state->range_startk = 0; @@ -356,7 +356,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) state->hole_sizek = 0; #endif } - /* Allocate an msr */ + /* Allocate an msr */ printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); state->range_startk = basek; state->range_sizek = sizek; @@ -365,7 +365,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) void x86_setup_fixed_mtrrs(void) { /* Try this the simple way of incrementally adding together - * mtrrs. If this doesn't work out we can get smart again + * mtrrs. If this doesn't work out we can get smart again * and clear out the mtrrs. */ @@ -390,20 +390,20 @@ void x86_setup_fixed_mtrrs(void) void x86_setup_var_mtrrs(unsigned address_bits) /* this routine needs to know how many address bits a given processor - * supports. CPUs get grumpy when you set too many bits in + * supports. CPUs get grumpy when you set too many bits in * their mtrr registers :( I would generically call cpuid here * and find out how many physically supported but some cpus are * buggy, and report more bits then they actually support. */ { /* Try this the simple way of incrementally adding together - * mtrrs. If this doesn't work out we can get smart again + * mtrrs. If this doesn't work out we can get smart again * and clear out the mtrrs. */ struct var_mtrr_state var_state; /* Cache as many memory areas as possible */ - /* FIXME is there an algorithm for computing the optimal set of mtrrs? + /* FIXME is there an algorithm for computing the optimal set of mtrrs? * In some cases it is definitely possible to do better. */ var_state.range_startk = 0; @@ -431,7 +431,7 @@ void x86_setup_var_mtrrs(unsigned address_bits) } #endif /* Write the last range */ - var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, + var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits); #if CONFIG_VAR_MTRR_HOLE var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk, diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 4440d7bd8c..0bec349444 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -43,7 +43,7 @@ static void paging_on(void *pdp) ); } -void *map_2M_page(unsigned long page) +void *map_2M_page(unsigned long page) { struct pde { uint32_t addr_lo; @@ -56,7 +56,7 @@ void *map_2M_page(unsigned long page) #if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE<0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) /* - pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000, + pgtbl is too big, so use last one 1M before CONFIG_LB_MEM_TOP, otherwise for 8 way dual core with vga support will push stack and heap cross 0xa0000, and that region need to be used as vga font buffer. Please make sure set CONFIG_RAMTOP=0x200000 in MB Config */ struct pg_table *pgtbl = (struct pg_table*)0x100000; //1M diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 9a2dfa599e..980ea69f51 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -72,14 +72,14 @@ static int uart_can_tx_byte(void) static void uart_wait_to_tx_byte(void) { - while(!uart_can_tx_byte()) + while(!uart_can_tx_byte()) ; } static void uart_wait_until_sent(void) { while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; + ; } static void uart_tx_byte(unsigned char data) diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index 1b25c2d2f8..d5c7127a15 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -4,7 +4,7 @@ CPUS = 4; SECTIONS { - /* This is the actual SMM handler. + /* This is the actual SMM handler. * * We just put code, rodata, data and bss all in a row. */ @@ -43,7 +43,7 @@ SECTIONS . = 0xa8000 - (( CPUS - 1) * 0x400); .jumptable : { *(.jumptable) - } + } /DISCARD/ : { *(.comment) diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index b443e5c1fe..3dd0b14c5a 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -38,11 +38,11 @@ * | | * | | * +--------------------------------+ 0xa8400 - * | SMM Entry Node 0 (+ stack) | + * | SMM Entry Node 0 (+ stack) | * +--------------------------------+ 0xa8000 - * | SMM Entry Node 1 (+ stack) | - * | SMM Entry Node 2 (+ stack) | - * | SMM Entry Node 3 (+ stack) | + * | SMM Entry Node 1 (+ stack) | + * | SMM Entry Node 2 (+ stack) | + * | SMM Entry Node 3 (+ stack) | * | ... | * +--------------------------------+ 0xa7400 * | | @@ -56,7 +56,7 @@ /* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG * at which smm_handler_start lives. At the moment the handler - * lives right at 0xa0000, so the offset is 0. + * lives right at 0xa0000, so the offset is 0. */ #define SMM_HANDLER_OFFSET 0x0000 @@ -101,15 +101,15 @@ smm_handler_start: movl $LAPIC_ID, %esi movl (%esi), %ecx shr $24, %ecx - + /* calculate stack offset by multiplying the APIC ID * by 1024 (0x400), and save that offset in ebp. */ shl $10, %ecx movl %ecx, %ebp - /* We put the stack for each core right above - * its SMM entry point. Core 0 starts at 0xa8000, + /* We put the stack for each core right above + * its SMM entry point. Core 0 starts at 0xa8000, * we spare 0x10 bytes for the jump to be sure. */ movl $0xa8010, %eax @@ -155,11 +155,11 @@ smm_gdt: .long 0x00000000, 0x00000000 /* gdt selector 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ /* gdt selector 0x10, flat data segment */ - .word 0xffff, 0x0000 + .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 smm_gdt_end: @@ -168,7 +168,7 @@ smm_gdt_end: .section ".jumptable", "a", @progbits /* This is the SMM jump table. All cores use the same SMM handler - * for simplicity. But SMM Entry needs to be different due to the + * for simplicity. But SMM Entry needs to be different due to the * save state area. The jump table makes sure all CPUs jump into the * real handler on SMM entry. */ @@ -185,13 +185,13 @@ smm_gdt_end: .code16 jumptable: /* core 3 */ - ljmp $0xa000, $SMM_HANDLER_OFFSET + ljmp $0xa000, $SMM_HANDLER_OFFSET .align 1024, 0x00 /* core 2 */ - ljmp $0xa000, $SMM_HANDLER_OFFSET + ljmp $0xa000, $SMM_HANDLER_OFFSET .align 1024, 0x00 /* core 1 */ - ljmp $0xa000, $SMM_HANDLER_OFFSET + ljmp $0xa000, $SMM_HANDLER_OFFSET .align 1024, 0x00 /* core 0 */ ljmp $0xa000, $SMM_HANDLER_OFFSET diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 14fdc639bc..50a8f28c3f 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -22,7 +22,7 @@ // Make sure no stage 2 code is included: #define __PRE_RAM__ -// FIXME: Is this piece of code southbridge specific, or +// FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? // It's needed right now because we get our PM_BASE from // here. @@ -73,7 +73,7 @@ * 0xa0000-0xa0400 and the stub plus stack would need to go * at 0xa8000-0xa8100 (example for core 0). That is not enough. * - * This means we're basically limited to 16 cpu cores before + * This means we're basically limited to 16 cpu cores before * we need to use the TSEG/HSEG for the actual SMM handler plus stack. * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG. * @@ -101,7 +101,7 @@ smm_relocation_start: addr32 mov (%ebx), %al cmp $0x64, %al je 1f - + mov $0x38000 + 0x7ef8, %ebx jmp smm_relocate 1: @@ -112,8 +112,8 @@ smm_relocate: movl $LAPIC_ID, %esi addr32 movl (%esi), %ecx shr $24, %ecx - - /* calculate offset by multiplying the + + /* calculate offset by multiplying the * apic ID by 1024 (0x400) */ movl %ecx, %edx @@ -158,7 +158,7 @@ smm_relocate: outb %al, %dx /* calculate ascii of cpu number. More than 9 cores? -> FIXME */ movb %cl, %al - addb $'0', %al + addb $'0', %al outb %al, %dx mov $']', %al outb %al, %dx diff --git a/src/cpu/x86/sse_disable.inc b/src/cpu/x86/sse_disable.inc index a18ea18643..a42cb41259 100644 --- a/src/cpu/x86/sse_disable.inc +++ b/src/cpu/x86/sse_disable.inc @@ -2,7 +2,7 @@ * Put the processor back into a reset state * with respect to the xmm registers. */ - + xorps %xmm0, %xmm0 xorps %xmm1, %xmm1 xorps %xmm2, %xmm2 diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 4a8fd5287e..27c89e3a94 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -10,7 +10,7 @@ static unsigned long clocks_per_usec; #if (CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 == 1) #define CLOCK_TICK_RATE 1193180U /* Underlying HZ */ -/* ------ Calibrate the TSC ------- +/* ------ Calibrate the TSC ------- * Too much 64-bit arithmetic here to do this cleanly in C, and for * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2) * output busy loop as low as possible. We avoid reading the CTC registers @@ -88,13 +88,13 @@ bad_ctc: * this is the "no timer2" version. * to calibrate tsc, we get a TSC reading, then do 1,000,000 outbs to port 0x80 * then we read TSC again, and divide the difference by 1,000,000 - * we have found on a wide range of machines that this gives us a a + * we have found on a wide range of machines that this gives us a a * good microsecond value * to +- 10%. On a dual AMD 1.6 Ghz box, it gives us .97 microseconds, and on a * 267 Mhz. p5, it gives us 1.1 microseconds. * also, since gcc now supports long long, we use that. * also no unsigned long long / operator, so we play games. - * about the only thing you can do with long longs, it seems, + * about the only thing you can do with long longs, it seems, *is return them and assign them. * (and do asm on them, yuck) * so avoid all ops on long longs. @@ -103,7 +103,7 @@ static unsigned long long calibrate_tsc(void) { unsigned long long start, end, delta; unsigned long result, count; - + printk(BIOS_SPEW, "Calibrating delay loop...\n"); start = rdtscll(); // no udivdi3 because we don't like libgcc. (only in x86emu) @@ -130,7 +130,7 @@ static unsigned long long calibrate_tsc(void) result = delta; printk(BIOS_SPEW, "end %llx, start %llx\n", end, start); printk(BIOS_SPEW, "32-bit delta %ld\n", (unsigned long) delta); - + printk(BIOS_SPEW, "%s 32-bit result is %ld\n", __func__, result); diff --git a/src/devices/cardbus_device.c b/src/devices/cardbus_device.c index becdafd42f..044dfd274f 100644 --- a/src/devices/cardbus_device.c +++ b/src/devices/cardbus_device.c @@ -159,8 +159,8 @@ void cardbus_enable_resources(device_t dev) uint16_t ctrl; ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); ctrl |= (dev->link[0].bridge_ctrl & ( - PCI_BRIDGE_CTL_PARITY | - PCI_BRIDGE_CTL_SERR | + PCI_BRIDGE_CTL_PARITY | + PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_NO_ISA | PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_MASTER_ABORT | @@ -174,8 +174,8 @@ void cardbus_enable_resources(device_t dev) enable_childrens_resources(dev); } -unsigned int cardbus_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, +unsigned int cardbus_scan_bus(struct bus *bus, + unsigned min_devfn, unsigned max_devfn, unsigned int max) { return pci_scan_bus(bus, min_devfn, max_devfn, max); @@ -196,7 +196,7 @@ unsigned int cardbus_scan_bridge(device_t dev, unsigned int max) /* Set up the primary, secondary and subordinate bus numbers. We have * no idea how many buses are behind this bridge yet, so we set the - * subordinate bus number to 0xff for the moment. + * subordinate bus number to 0xff for the moment. */ bus->secondary = ++max; bus->subordinate = 0xff; @@ -222,7 +222,7 @@ unsigned int cardbus_scan_bridge(device_t dev, unsigned int max) ((unsigned int) (bus->subordinate) << 16)); pci_write_config32(dev, PCI_CB_PRIMARY_BUS, buses); - /* Now we can scan all subordinate buses + /* Now we can scan all subordinate buses * i.e. the bus behind the bridge. */ max = cardbus_scan_bus(bus, 0x00, 0xff, max); @@ -235,7 +235,7 @@ unsigned int cardbus_scan_bridge(device_t dev, unsigned int max) ((unsigned int) (bus->subordinate) << 16); pci_write_config32(dev, PCI_CB_PRIMARY_BUS, buses); pci_write_config16(dev, PCI_COMMAND, cr); - + printk(BIOS_SPEW, "%s returns max %d\n", __func__, max); return max; } diff --git a/src/devices/device_util.c b/src/devices/device_util.c index e44a02e428..3e8cba2f98 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -79,7 +79,7 @@ struct device *dev_find_slot(unsigned int bus, unsigned int devfn) result = 0; for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_PCI) && - (dev->bus->secondary == bus) && + (dev->bus->secondary == bus) && (dev->path.pci.devfn == devfn)) { result = dev; break; @@ -92,32 +92,32 @@ struct device *dev_find_slot(unsigned int bus, unsigned int devfn) * @brief Given a smbus bus and a device number, find the device structure * * @param bus The bus number - * @param addr a device number + * @param addr a device number * @return pointer to the device structure */ struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr) { struct device *dev, *result; - + result = 0; for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_I2C) && - (dev->bus->secondary == bus) && + (dev->bus->secondary == bus) && (dev->path.i2c.device == addr)) { result = dev; - break; - } - } + break; + } + } return result; -} +} /** Find a device of a given vendor and type * @param vendor Vendor ID (e.g. 0x8086 for Intel) * @param device Device ID * @param from Pointer to the device structure, used as a starting point - * in the linked list of all_devices, which can be 0 to start at the + * in the linked list of all_devices, which can be 0 to start at the * head of the list (i.e. all_devices) - * @return Pointer to the device struct + * @return Pointer to the device struct */ struct device *dev_find_device(unsigned int vendor, unsigned int device, struct device *from) { @@ -134,9 +134,9 @@ struct device *dev_find_device(unsigned int vendor, unsigned int device, struct /** Find a device of a given class * @param class Class of the device * @param from Pointer to the device structure, used as a starting point - * in the linked list of all_devices, which can be 0 to start at the + * in the linked list of all_devices, which can be 0 to start at the * head of the list (i.e. all_devices) - * @return Pointer to the device struct + * @return Pointer to the device struct */ struct device *dev_find_class(unsigned int class, struct device *from) { @@ -167,11 +167,11 @@ const char *dev_path(device_t dev) case DEVICE_PATH_PCI: #if CONFIG_PCI_BUS_SEGN_BITS sprintf(buffer, "PCI: %04x:%02x:%02x.%01x", - dev->bus->secondary>>8, dev->bus->secondary & 0xff, + dev->bus->secondary>>8, dev->bus->secondary & 0xff, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); #else sprintf(buffer, "PCI: %02x:%02x.%01x", - dev->bus->secondary, + dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); #endif break; @@ -408,7 +408,7 @@ resource_t resource_end(struct resource *resource) * the bridge. While the granularity is simply how many low bits of the * address cannot be set. */ - + /* Get the end (rounded up) */ end = base + align_up(resource->size, resource->gran) - 1; @@ -468,7 +468,7 @@ void report_resource_stored(device_t dev, struct resource *resource, const char sprintf(buf, "bus %02x ", dev->link[0].secondary); #endif } - printk(BIOS_DEBUG, + printk(BIOS_DEBUG, "%s %02lx <- [0x%010Lx - 0x%010Lx] size 0x%08Lx gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, diff --git a/src/devices/hypertransport.c b/src/devices/hypertransport.c index bb91249908..674971cb94 100644 --- a/src/devices/hypertransport.c +++ b/src/devices/hypertransport.c @@ -39,7 +39,7 @@ * so don't do it again */ #define OPT_HT_LINK 0 - + #if OPT_HT_LINK == 1 #include #endif @@ -52,9 +52,9 @@ static device_t ht_scan_get_devs(device_t *old_devices) /* Extract the chain of devices to (first through last) * for the next hypertransport device. */ - while(last && last->sibling && + while(last && last->sibling && (last->sibling->path.type == DEVICE_PATH_PCI) && - (last->sibling->path.pci.devfn > last->path.pci.devfn)) + (last->sibling->path.pci.devfn > last->path.pci.devfn)) { last = last->sibling; } @@ -101,11 +101,11 @@ static unsigned ht_read_freq_cap(device_t dev, unsigned pos) } /* AMD K8 Unsupported 1Ghz? */ if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) { -#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 - #if CONFIG_K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_e0()) { // only e0 later suupport 1GHz HT freq_cap &= ~(1 << HT_FREQ_1000Mhz); - } + } #endif #else freq_cap &= ~(1 << HT_FREQ_1000Mhz); @@ -129,7 +129,7 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; unsigned present_width_cap, upstream_width_cap; unsigned present_freq_cap, upstream_freq_cap; - unsigned ln_present_width_in, ln_upstream_width_in; + unsigned ln_present_width_in, ln_upstream_width_in; unsigned ln_present_width_out, ln_upstream_width_out; unsigned freq, old_freq; unsigned present_width, upstream_width, old_width; @@ -140,7 +140,7 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) /* Set the hypertransport link width and frequency */ reset_needed = 0; - /* See which side of the device our previous write to + /* See which side of the device our previous write to * set the unitid came from. */ cur->dev = dev; @@ -164,7 +164,7 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) upstream_freq_cap = ht_read_freq_cap(prev->dev, prev->pos + prev->freq_cap_off); present_width_cap = pci_read_config8(cur->dev, cur->pos + cur->config_off); upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off); - + /* Calculate the highest useable frequency */ freq = log2(present_freq_cap & upstream_freq_cap); @@ -242,7 +242,7 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) } } #endif - + /* Remember the current link as the previous link, * But look at the other offsets. */ @@ -261,7 +261,7 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) } return reset_needed; - + } static unsigned ht_lookup_slave_capability(struct device *dev) @@ -355,7 +355,7 @@ static void ht_collapse_early_enumeration(struct bus *bus, unsigned offset_uniti dummy.path.type = DEVICE_PATH_PCI; dummy.path.pci.devfn = devfn; id = pci_read_config32(&dummy, PCI_VENDOR_ID); - if ( (id == 0xffffffff) || (id == 0x00000000) || + if ( (id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { continue; } @@ -371,12 +371,12 @@ static void ht_collapse_early_enumeration(struct bus *bus, unsigned offset_uniti flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS); flags &= ~0x1f; pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags); - printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n", + printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n", dev_path(&dummy), dummy.vendor, dummy.device); } } -unsigned int hypertransport_scan_chain(struct bus *bus, +unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unitid_base, unsigned offset_unitid) { //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link @@ -410,7 +410,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, prev.config_off = PCI_HT_CAP_HOST_WIDTH; prev.freq_off = PCI_HT_CAP_HOST_FREQ; prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP; - + /* If present assign unitid to a hypertransport chain */ last_unitid = min_unitid -1; max_unitid = next_unitid = min_unitid; @@ -446,7 +446,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, } } } while((ctrl & (1 << 5)) == 0); - + /* Get and setup the device_structure */ dev = ht_scan_get_devs(&old_devices); @@ -462,15 +462,15 @@ unsigned int hypertransport_scan_chain(struct bus *bus, /* Find the hypertransport link capability */ pos = ht_lookup_slave_capability(dev); if (pos == 0) { - printk(BIOS_ERR, "%s Hypertransport link capability not found", + printk(BIOS_ERR, "%s Hypertransport link capability not found", dev_path(dev)); break; } - + /* Update the Unitid of the current device */ flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); - - /* If the devices has a unitid set and is at devfn 0 we are done. + + /* If the devices has a unitid set and is at devfn 0 we are done. * This can happen with shadow hypertransport devices, * or if we have reached the bottom of a * hypertransport device chain. @@ -492,7 +492,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, } } - } + } #endif flags |= next_unitid & 0x1f; @@ -502,12 +502,12 @@ unsigned int hypertransport_scan_chain(struct bus *bus, static_count = 1; for(func = dev; func; func = func->sibling) { func->path.pci.devfn += (next_unitid << 3); - static_count = (func->path.pci.devfn >> 3) + static_count = (func->path.pci.devfn >> 3) - (dev->path.pci.devfn >> 3) + 1; last_func = func; } /* Compute the number of unitids consumed */ - printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n", + printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n", dev_path(dev), count, static_count); if (count < static_count) { count = static_count; @@ -534,7 +534,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n", dev_path(dev), - dev->vendor, dev->device, + dev->vendor, dev->device, (dev->enabled? "enabled": "disabled"), next_unitid); } while (last_unitid != next_unitid); @@ -562,7 +562,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, } ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; // update last one - + printk(BIOS_DEBUG, " unitid: %04x --> %04x\n", real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE); @@ -573,11 +573,11 @@ unsigned int hypertransport_scan_chain(struct bus *bus, if (next_unitid > 0x20) { next_unitid = 0x20; } - if( (bus->secondary == 0) && (next_unitid > 0x18)) { + if( (bus->secondary == 0) && (next_unitid > 0x18)) { next_unitid = 0x18; /* avoid K8 on bus 0 */ } - /* Die if any leftover Static devices are are found. + /* Die if any leftover Static devices are are found. * There's probably a problem in the Config.lb. */ if(old_devices) { @@ -587,14 +587,14 @@ unsigned int hypertransport_scan_chain(struct bus *bus, } printk(BIOS_ERR, "HT: Left over static devices. Check your Config.lb\n"); if(last_func && !last_func->sibling) // put back the left over static device, and let pci_scan_bus disable it - last_func->sibling = old_devices; + last_func->sibling = old_devices; } /* Now that nothing is overlapping it is safe to scan the - * children. + * children. */ - max = pci_scan_bus(bus, 0x00, ((next_unitid-1) << 3)|7, max); - return max; + max = pci_scan_bus(bus, 0x00, ((next_unitid-1) << 3)|7, max); + return max; } /** diff --git a/src/devices/oprom/include/x86emu/regs.h b/src/devices/oprom/include/x86emu/regs.h index 516b2ea836..d738974d4b 100644 --- a/src/devices/oprom/include/x86emu/regs.h +++ b/src/devices/oprom/include/x86emu/regs.h @@ -106,7 +106,7 @@ struct i386_special_regs { u32 FLAGS; }; -/* +/* * Segment registers here represent the 16 bit quantities * CS, DS, ES, SS. */ @@ -184,8 +184,8 @@ struct i386_segment_regs { #define F_ALWAYS_ON (0x0002) /* flag bits always on */ /* - * Define a mask for only those flag bits we will ever pass back - * (via PUSHF) + * Define a mask for only those flag bits we will ever pass back + * (via PUSHF) */ #define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) @@ -271,8 +271,8 @@ typedef struct { * Delayed flag set 3 bits (zero, signed, parity) * reserved 6 bits * interrupt # 8 bits instruction raised interrupt - * BIOS video segregs 4 bits - * Interrupt Pending 1 bits + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits * Extern interrupt 1 bits * Halted 1 bits */ diff --git a/src/devices/oprom/include/x86emu/x86emu.h b/src/devices/oprom/include/x86emu/x86emu.h index 493e494927..3ceee4985b 100644 --- a/src/devices/oprom/include/x86emu/x86emu.h +++ b/src/devices/oprom/include/x86emu/x86emu.h @@ -128,7 +128,7 @@ extern u32 X86API rdl(u32 addr); extern void X86API wrb(u32 addr, u8 val); extern void X86API wrw(u32 addr, u16 val); extern void X86API wrl(u32 addr, u32 val); - + #pragma pack() /*--------------------- type definitions -----------------------------------*/ @@ -175,10 +175,10 @@ void X86EMU_halt_sys(void); #define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ #define DEBUG_TRACECALL_F 0x000400 #define DEBUG_INSTRUMENT_F 0x000800 -#define DEBUG_MEM_TRACE_F 0x001000 -#define DEBUG_IO_TRACE_F 0x002000 +#define DEBUG_MEM_TRACE_F 0x001000 +#define DEBUG_IO_TRACE_F 0x002000 #define DEBUG_TRACECALL_REGS_F 0x004000 -#define DEBUG_DECODE_NOPRINT_F 0x008000 +#define DEBUG_DECODE_NOPRINT_F 0x008000 #define DEBUG_SAVE_IP_CS_F 0x010000 #define DEBUG_TRACEJMP_F 0x020000 #define DEBUG_TRACEJMP_REGS_F 0x040000 diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c index 9e72a4a6a6..4d9604a581 100644 --- a/src/devices/oprom/x86.c +++ b/src/devices/oprom/x86.c @@ -45,16 +45,16 @@ int (*intXX_handler[256])(struct eregs *regs) = { NULL }; static int intXX_exception_handler(struct eregs *regs) { - printk(BIOS_INFO, "Oops, exception %d while executing option rom\n", + printk(BIOS_INFO, "Oops, exception %d while executing option rom\n", regs->vector); - x86_exception(regs); // Call coreboot exception handler + x86_exception(regs); // Call coreboot exception handler return 0; // Never returns? } static int intXX_unknown_handler(struct eregs *regs) { - printk(BIOS_INFO, "Unsupported software interrupt #0x%x\n", + printk(BIOS_INFO, "Unsupported software interrupt #0x%x\n", regs->vector); return -1; @@ -74,12 +74,12 @@ static void setup_interrupt_handlers(void) { int i; - /* The first 16 intXX functions are not BIOS services, + /* The first 16 intXX functions are not BIOS services, * but the CPU-generated exceptions ("hardware interrupts") */ for (i = 0; i < 0x10; i++) intXX_handler[i] = &intXX_exception_handler; - + /* Mark all other intXX calls as unknown first */ for (i = 0x10; i < 0x100; i++) { @@ -133,14 +133,14 @@ static void setup_realmode_idt(void) } /* Many option ROMs use the hard coded interrupt entry points in the - * system bios. So install them at the known locations. + * system bios. So install them at the known locations. */ - + /* int42 is the relocated int10 */ write_idt_stub((void *)0xff065, 0x42); /* VIA's VBIOS calls f000:f859 instead of int15 */ - write_idt_stub((void *)0xff859, 0x15); + write_idt_stub((void *)0xff859, 0x15); } void run_bios(struct device *dev, unsigned long addr) @@ -187,7 +187,7 @@ static u32 VSA_vrRead(u16 classIndex) "outl %%eax, %%dx\n" "addb $2, %%dl\n" "inw %%dx, %%ax\n" - : "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) + : "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) : "a"(classIndex) ); @@ -245,7 +245,7 @@ void do_vsmbios(void) } #endif -/* interrupt_handler() is called from assembler code only, +/* interrupt_handler() is called from assembler code only, * so there is no use in putting the prototype into a header file. */ int __attribute__((regparm(0))) interrupt_handler(u32 intnumber, @@ -308,7 +308,7 @@ int __attribute__((regparm(0))) interrupt_handler(u32 intnumber, // will later pop them. // What happens here is that we force (volatile!) changing // the values of the parameters of this function. We do this - // because we know that they stay alive on the stack after + // because we know that they stay alive on the stack after // we leave this function. Don't say this is bollocks. *(volatile u32 *)&eax = reg_info.eax; *(volatile u32 *)&ecx = reg_info.ecx; diff --git a/src/devices/oprom/x86_asm.S b/src/devices/oprom/x86_asm.S index 724fe02c0d..469c42f90b 100644 --- a/src/devices/oprom/x86_asm.S +++ b/src/devices/oprom/x86_asm.S @@ -25,7 +25,7 @@ /* This is the intXX interrupt handler stub code. It gets copied * to the IDT and to some fixed addresses in the F segment. Before - * the code can used, it gets patched up by the C function copying + * the code can used, it gets patched up by the C function copying * it: byte 3 (the $0 in movb $0, %al) is overwritten with the int#. */ @@ -85,11 +85,11 @@ __run_optionrom = RELOCATED(.) * protected mode is turned off. */ mov $0x30, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss /* Turn off protection */ movl %cr0, %eax @@ -114,9 +114,9 @@ __run_optionrom = RELOCATED(.) lidt __realmode_idt /* Set all segments to 0x0000, ds to 0x0040 */ - mov %ax, %es - mov %ax, %fs - mov %ax, %gs + mov %ax, %es + mov %ax, %fs + mov %ax, %gs mov $0x40, %ax mov %ax, %ds @@ -140,8 +140,8 @@ __run_optionrom = RELOCATED(.) data32 ljmp $0x10, $RELOCATED(1f) 1: .code32 - movw $0x18, %ax - mov %ax, %ds + movw $0x18, %ax + mov %ax, %ds mov %ax, %es mov %ax, %fs mov %ax, %gs @@ -185,11 +185,11 @@ __run_vsa = RELOCATED(.) * protected mode is turned off. */ mov $0x30, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss /* Turn off protection */ movl %cr0, %eax @@ -214,9 +214,9 @@ __run_vsa = RELOCATED(.) lidt __realmode_idt /* Set all segments to 0x0000, ds to 0x0040 */ - mov %ax, %es - mov %ax, %fs - mov %ax, %gs + mov %ax, %es + mov %ax, %fs + mov %ax, %gs mov $0x40, %ax mov %ax, %ds mov %cx, %ax // restore ax @@ -238,8 +238,8 @@ __run_vsa = RELOCATED(.) data32 ljmp $0x10, $RELOCATED(1f) 1: .code32 - movw $0x18, %ax - mov %ax, %ds + movw $0x18, %ax + mov %ax, %ds mov %ax, %es mov %ax, %fs mov %ax, %gs @@ -275,17 +275,17 @@ __run_interrupt = RELOCATED(.) * descriptors. They will retain these configurations (limits, * writability, etc.) once protected mode is turned off. */ - mov $0x30, %ax - mov %ax, %ds - mov %ax, %es - mov %ax, %fs - mov %ax, %gs - mov %ax, %ss + mov $0x30, %ax + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss /* Turn off protected mode */ - movl %cr0, %eax + movl %cr0, %eax andl $~PE, %eax - movl %eax, %cr0 + movl %eax, %cr0 /* Now really going into real mode */ data32 ljmp $0, $RELOCATED(1f) @@ -302,7 +302,7 @@ __run_interrupt = RELOCATED(.) movl %eax, %esp /* Load 16-bit intXX IDT */ - xor %ax, %ax + xor %ax, %ax mov %ax, %ds lidt __realmode_idt diff --git a/src/devices/oprom/x86_interrupts.c b/src/devices/oprom/x86_interrupts.c index 90156334dc..49d69ee3a7 100644 --- a/src/devices/oprom/x86_interrupts.c +++ b/src/devices/oprom/x86_interrupts.c @@ -202,7 +202,7 @@ int int15_handler(struct eregs *regs) res = 0; break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); } diff --git a/src/devices/oprom/x86emu/decode.c b/src/devices/oprom/x86emu/decode.c index 3d2ba23566..ed96dc66e6 100644 --- a/src/devices/oprom/x86emu/decode.c +++ b/src/devices/oprom/x86emu/decode.c @@ -732,7 +732,7 @@ RETURNS: Value of scale * index REMARKS: -Decodes scale/index of SIB byte and returns relevant offset part of +Decodes scale/index of SIB byte and returns relevant offset part of effective address. ****************************************************************************/ static unsigned decode_sib_si( diff --git a/src/devices/oprom/x86emu/ops2.c b/src/devices/oprom/x86emu/ops2.c index f5cb6498b1..349a664f50 100644 --- a/src/devices/oprom/x86emu/ops2.c +++ b/src/devices/oprom/x86emu/ops2.c @@ -170,7 +170,7 @@ static void x86emuOp2_rdmsr(u8 op2) M.x86.R_EAX = 0; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); -} +} #define xorl(a,b) (((a) && !(b)) || (!(a) && (b))) diff --git a/src/devices/oprom/x86emu/sys.c b/src/devices/oprom/x86emu/sys.c index 957e0ca63b..7a9e3921ec 100644 --- a/src/devices/oprom/x86emu/sys.c +++ b/src/devices/oprom/x86emu/sys.c @@ -85,7 +85,7 @@ RETURNS: Byte value read from emulator memory. REMARKS: -Reads a byte value from the emulator memory. +Reads a byte value from the emulator memory. ****************************************************************************/ u8 X86API rdb(u32 addr) { @@ -130,7 +130,7 @@ addr - Emulator memory address to read RETURNS: Long value read from emulator memory. REMARKS: -Reads a long value from the emulator memory. +Reads a long value from the emulator memory. ****************************************************************************/ u32 X86API rdl(u32 addr) { @@ -189,7 +189,7 @@ addr - Emulator memory address to read val - Value to store REMARKS: -Writes a long value to emulator memory. +Writes a long value to emulator memory. ****************************************************************************/ void X86API wrl(u32 addr, u32 val) { diff --git a/src/devices/oprom/x86emu/x86emui.h b/src/devices/oprom/x86emu/x86emui.h index d693e335f4..8ad43bfa30 100644 --- a/src/devices/oprom/x86emu/x86emui.h +++ b/src/devices/oprom/x86emu/x86emui.h @@ -75,7 +75,7 @@ #include #else #include -#endif +#endif /*--------------------------- Inline Functions ----------------------------*/ #ifdef __cplusplus diff --git a/src/devices/oprom/yabel/biosemu.c b/src/devices/oprom/yabel/biosemu.c index 294d81f279..9cdd0f279b 100644 --- a/src/devices/oprom/yabel/biosemu.c +++ b/src/devices/oprom/yabel/biosemu.c @@ -250,7 +250,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad X86EMU_setupMemFuncs(&my_mem_funcs); //setup PMM struct in BIOS_DATA_SEGMENT, offset 0x0 - u8 pmm_length = pmm_setup(BIOS_DATA_SEGMENT, 0x0); + u8 pmm_length = pmm_setup(BIOS_DATA_SEGMENT, 0x0); if (pmm_length <= 0) { printf ("\nYABEL: Warning: PMM Area could not be setup. PMM not available (%x)\n", pmm_length); diff --git a/src/devices/oprom/yabel/biosemu.h b/src/devices/oprom/yabel/biosemu.h index 09ace729ec..39cc0a9b0e 100644 --- a/src/devices/oprom/yabel/biosemu.h +++ b/src/devices/oprom/yabel/biosemu.h @@ -38,7 +38,7 @@ // Address, there will only be a call to this INT and a RETF #define PNP_INT_NUM 0xFD -/* array of funtion pointers to override generic interrupt handlers +/* array of funtion pointers to override generic interrupt handlers * a YABEL caller can add functions to this array before calling YABEL * if a interrupt occurs, YABEL checks wether a function is set in * this array and only runs the generic interrupt handler code, if diff --git a/src/devices/oprom/yabel/compat/functions.c b/src/devices/oprom/yabel/compat/functions.c index 035c8bc86e..c9ef0b7d77 100644 --- a/src/devices/oprom/yabel/compat/functions.c +++ b/src/devices/oprom/yabel/compat/functions.c @@ -61,6 +61,6 @@ u64 get_time(void) "rdtsc" : "=a"(eax), "=d"(edx) : /* no inputs, no clobber */); - act = ((u64) edx << 32) | eax; + act = ((u64) edx << 32) | eax; return act; } diff --git a/src/devices/oprom/yabel/compat/of.h b/src/devices/oprom/yabel/compat/of.h index 907139951f..6a00f7a316 100644 --- a/src/devices/oprom/yabel/compat/of.h +++ b/src/devices/oprom/yabel/compat/of.h @@ -19,7 +19,7 @@ #define phandle_t p32 #define ihandle_t p32 -typedef struct +typedef struct { unsigned int serv; int nargs; diff --git a/src/devices/oprom/yabel/compat/time.h b/src/devices/oprom/yabel/compat/time.h index 6f7099bd86..18dba3aa85 100644 --- a/src/devices/oprom/yabel/compat/time.h +++ b/src/devices/oprom/yabel/compat/time.h @@ -15,4 +15,4 @@ /* TODO: check how this works in x86 */ extern unsigned long tb_freq; u64 get_time(void); -#endif +#endif diff --git a/src/devices/oprom/yabel/debug.h b/src/devices/oprom/yabel/debug.h index d02930809d..fea1fb7a3b 100644 --- a/src/devices/oprom/yabel/debug.h +++ b/src/devices/oprom/yabel/debug.h @@ -39,7 +39,7 @@ static inline void set_ci(void) {}; * |||-Currently unused * ||||-Currently unused * |||||-Currently unused - * ||||||-DEBUG_PNP - Print Plug And Play access made by option rom + * ||||||-DEBUG_PNP - Print Plug And Play access made by option rom * |||||||-DEBUG_DISK - Print Disk I/O related messages, currently unused * ||||||||-DEBUG_PMM - Print messages related to POST Memory Manager (PMM) * |||||||||-DEBUG_VBE - Print messages related to VESA BIOS Extension (VBE) functions @@ -47,7 +47,7 @@ static inline void set_ci(void) {}; * |||||||||||-DEBUG_INTR - Print messages related to interrupt handling * ||||||||||||-DEBUG_CHECK_VMEM_ACCESS - Print messages related to accesse to certain areas of the virtual Memory (e.g. BDA (BIOS Data Area) or Interrupt Vectors) * |||||||||||||-DEBUG_MEM - Print memory access made by option rom (NOTE: this also includes accesses to fetch instructions) - * ||||||||||||||-DEBUG_IO - Print I/O access made by option rom + * ||||||||||||||-DEBUG_IO - Print I/O access made by option rom * 11000111111111 - Max Binary Value, Debug All (WARNING: - This could run for hours) */ diff --git a/src/devices/oprom/yabel/interrupt.c b/src/devices/oprom/yabel/interrupt.c index 9a796005bb..af79379f67 100644 --- a/src/devices/oprom/yabel/interrupt.c +++ b/src/devices/oprom/yabel/interrupt.c @@ -410,7 +410,7 @@ handleInt1a(void) M.x86.R_CL = #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config8(dev, offs); -#else +#else (u8) rtas_pci_config_read(bios_device. puid, 1, bus, devfn, @@ -425,7 +425,7 @@ handleInt1a(void) M.x86.R_CX = #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config16(dev, offs); -#else +#else (u16) rtas_pci_config_read(bios_device. puid, 2, bus, devfn, @@ -440,7 +440,7 @@ handleInt1a(void) M.x86.R_ECX = #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config32(dev, offs); -#else +#else (u32) rtas_pci_config_read(bios_device. puid, 4, bus, devfn, @@ -478,7 +478,7 @@ handleInt1a(void) case 0xb10b: #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config8(bios_device.dev, offs, M.x86.R_CL); -#else +#else rtas_pci_config_write(bios_device.puid, 1, bus, devfn, offs, M.x86.R_CL); #endif @@ -490,7 +490,7 @@ handleInt1a(void) case 0xb10c: #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config16(bios_device.dev, offs, M.x86.R_CX); -#else +#else rtas_pci_config_write(bios_device.puid, 2, bus, devfn, offs, M.x86.R_CX); #endif @@ -502,7 +502,7 @@ handleInt1a(void) case 0xb10d: #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config32(bios_device.dev, offs, M.x86.R_ECX); -#else +#else rtas_pci_config_write(bios_device.puid, 4, bus, devfn, offs, M.x86.R_ECX); #endif @@ -576,7 +576,7 @@ handleInterrupt(int intNum) int_handled = 1; break; case PMM_INT_NUM: - /* the selfdefined PMM INT number, this is called by the code in PMM struct, it + /* the selfdefined PMM INT number, this is called by the code in PMM struct, it * is handled by pmm_handleInt() */ pmm_handleInt(); diff --git a/src/devices/oprom/yabel/pmm.c b/src/devices/oprom/yabel/pmm.c index ad4dc6834c..989bde4d27 100644 --- a/src/devices/oprom/yabel/pmm.c +++ b/src/devices/oprom/yabel/pmm.c @@ -19,8 +19,8 @@ #include "device.h" /* this struct is used to remember which PMM spaces - * have been assigned. MAX_PMM_AREAS defines how many - * PMM areas we can assign. + * have been assigned. MAX_PMM_AREAS defines how many + * PMM areas we can assign. * All areas are assigned in PMM_CONV_SEGMENT */ typedef struct { @@ -37,7 +37,7 @@ static pmm_allocation_t pmm_allocation_array[MAX_PMM_AREAS]; /* index into pmm_allocation_array */ static u32 curr_pmm_allocation_index = 0; -/* This function is used to setup the PMM struct in virtual memory +/* This function is used to setup the PMM struct in virtual memory * at a certain offset, the length of the PMM struct is returned */ u8 pmm_setup(u16 segment, u16 offset) { @@ -79,7 +79,7 @@ u8 pmm_setup(u16 segment, u16 offset) return sizeof(pmm_information_t); } -/* handle the selfdefined interrupt, this is executed, when the PMM Entry Point +/* handle the selfdefined interrupt, this is executed, when the PMM Entry Point * is executed, it must handle all PMM requests */ void pmm_handleInt() @@ -136,7 +136,7 @@ void pmm_handleInt() __func__, next_offset); if (length == 0) { /* largest possible block size requested, we have on segment - * to allocate, so largest possible is segment size (0xFFFF) + * to allocate, so largest possible is segment size (0xFFFF) * minus next_offset */ rval = 0xFFFF - next_offset; @@ -151,7 +151,7 @@ void pmm_handleInt() } align = 1 << lsb; } - /* always align at least to paragraph (16byte) boundary + /* always align at least to paragraph (16byte) boundary * hm... since the length is always in paragraphs, we cannot * align outside of paragraphs anyway... so this check might * be unnecessary...*/ diff --git a/src/devices/oprom/yabel/pmm.h b/src/devices/oprom/yabel/pmm.h index 95645dffdc..3cc3c17ac6 100644 --- a/src/devices/oprom/yabel/pmm.h +++ b/src/devices/oprom/yabel/pmm.h @@ -34,7 +34,7 @@ typedef struct { u8 code[3]; } __attribute__ ((__packed__)) pmm_information_t; -/* This function is used to setup the PMM struct in virtual memory +/* This function is used to setup the PMM struct in virtual memory * at a certain offset */ u8 pmm_setup(u16 segment, u16 offset); diff --git a/src/devices/oprom/yabel/vbe.c b/src/devices/oprom/yabel/vbe.c index d80a97acc6..6ddeba613b 100644 --- a/src/devices/oprom/yabel/vbe.c +++ b/src/devices/oprom/yabel/vbe.c @@ -796,7 +796,7 @@ void vbe_set_graphics(void) mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE; vbe_get_mode_info(&mode_info); - unsigned char *framebuffer = + unsigned char *framebuffer = (unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr); DEBUG_PRINTF_VBE("FRAMEBUFFER: 0x%08x\n", framebuffer); vbe_set_mode(&mode_info); @@ -807,9 +807,9 @@ void vbe_set_graphics(void) /* Switching Intel IGD to 1MB video memory will break this. Who * cares. */ // int imagesize = 1024*768*2; - + unsigned char *jpeg = cbfs_find_file("bootsplash.jpg", CBFS_TYPE_BOOTSPLASH); - if (!jpeg) { + if (!jpeg) { DEBUG_PRINTF_VBE("Could not find bootsplash.jpg\n"); return; } diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index b85ee53a72..8863c237a4 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -1187,7 +1187,7 @@ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) #if CONFIG_PC80_SYSTEM == 1 /** - * + * * @brief Assign IRQ numbers * * This function assigns IRQs for all functions contained within the indicated @@ -1199,8 +1199,8 @@ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) * @param bus * @param slot * @param pIntAtoD is an array of IRQ #s that are assigned to PINTA through - * PINTD of this slot. The particular irq #s that are passed in - * depend on the routing inside your southbridge and on your + * PINTD of this slot. The particular irq #s that are passed in + * depend on the routing inside your southbridge and on your * motherboard. */ void pci_assign_irqs(unsigned bus, unsigned slot, @@ -1229,7 +1229,7 @@ void pci_assign_irqs(unsigned bus, unsigned slot, printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n", irq, bus, slot, funct); - pci_write_config8(pdev, PCI_INTERRUPT_LINE, + pci_write_config8(pdev, PCI_INTERRUPT_LINE, pIntAtoD[line - 1]); #ifdef PARANOID_IRQ_ASSIGNMENTS diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c index 0ed347b4e7..f13d9b6768 100644 --- a/src/devices/pci_rom.c +++ b/src/devices/pci_rom.c @@ -87,7 +87,7 @@ struct rom_header * pci_rom_probe(struct device *dev) rom_data->class_hi, rom_data->class_lo, rom_data->type); if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) { - printk(BIOS_DEBUG, "Class Code mismatch ROM %08x, dev %08x\n", + printk(BIOS_DEBUG, "Class Code mismatch ROM %08x, dev %08x\n", (rom_data->class_hi << 8) | rom_data->class_lo, dev->class); //return NULL; diff --git a/src/devices/pciexp_device.c b/src/devices/pciexp_device.c index a14f00426f..790029ef1e 100644 --- a/src/devices/pciexp_device.c +++ b/src/devices/pciexp_device.c @@ -46,8 +46,8 @@ static void pciexp_tune_dev(device_t dev) #endif } -unsigned int pciexp_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, +unsigned int pciexp_scan_bus(struct bus *bus, + unsigned min_devfn, unsigned max_devfn, unsigned int max) { device_t child; diff --git a/src/devices/pcix_device.c b/src/devices/pcix_device.c index e6147c9ba8..d3af53eed0 100644 --- a/src/devices/pcix_device.c +++ b/src/devices/pcix_device.c @@ -86,12 +86,12 @@ const char *pcix_speed(unsigned sstatus) static const char pcix_266mhz[] = "266MHz PCI-X"; static const char pcix_533mhz[] = "533MHZ PCI-X"; static const char unknown[] = "Unknown"; - + const char *result; result = unknown; switch(PCI_X_SSTATUS_MFREQ(sstatus)) { - case PCI_X_SSTATUS_CONVENTIONAL_PCI: - result = conventional; + case PCI_X_SSTATUS_CONVENTIONAL_PCI: + result = conventional; break; case PCI_X_SSTATUS_MODE1_66MHZ: result = pcix_66mhz; @@ -99,17 +99,17 @@ const char *pcix_speed(unsigned sstatus) case PCI_X_SSTATUS_MODE1_100MHZ: result = pcix_100mhz; break; - + case PCI_X_SSTATUS_MODE1_133MHZ: result = pcix_133mhz; break; - + case PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ: case PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ: case PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ: result = pcix_266mhz; break; - + case PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ: case PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ: case PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ: diff --git a/src/devices/pnp_device.c b/src/devices/pnp_device.c index 721d1ce3dc..469487d1d2 100644 --- a/src/devices/pnp_device.c +++ b/src/devices/pnp_device.c @@ -172,11 +172,11 @@ static void pnp_get_ioresource(device_t dev, unsigned index, struct io_info *inf unsigned moving, gran, step; resource = new_resource(dev, index); - + /* Initilize the resource */ resource->limit = 0xffff; resource->flags |= IORESOURCE_IO; - + /* Get the resource size */ moving = info->mask; gran = 15; @@ -259,9 +259,9 @@ static void get_resources(device_t dev, struct pnp_info *info) resource->size = 1; resource->flags |= IORESOURCE_IRQ; } -} +} -void pnp_enable_devices(device_t base_dev, struct device_operations *ops, +void pnp_enable_devices(device_t base_dev, struct device_operations *ops, unsigned functions, struct pnp_info *info) { struct device_path path; @@ -270,7 +270,7 @@ void pnp_enable_devices(device_t base_dev, struct device_operations *ops, path.type = DEVICE_PATH_PNP; path.pnp.port = base_dev->path.pnp.port; - + /* Setup the ops and resources on the newly allocated devices */ for(i = 0; i < functions; i++) { /* Skip logical devices this Super I/O doesn't have. */ @@ -279,9 +279,9 @@ void pnp_enable_devices(device_t base_dev, struct device_operations *ops, path.pnp.device = info[i].function; dev = alloc_find_dev(base_dev->bus, &path); - + /* Don't initialize a device multiple times */ - if (dev->ops) + if (dev->ops) continue; if (info[i].ops == 0) { diff --git a/src/devices/root_device.c b/src/devices/root_device.c index 3e3249e85e..b9369bcd1d 100644 --- a/src/devices/root_device.c +++ b/src/devices/root_device.c @@ -27,7 +27,7 @@ #include #include -/** +/** * Read the resources for the root device, * that encompass the resources for the entire system. * @param root Pointer to the device structure for the system root device @@ -54,9 +54,9 @@ void root_dev_set_resources(device_t root) * * The enumeration of certain buses is purely static. The existence of * devices on those buses can be completely determined at compile time - * and is specified in the config file. Typical examples are the 'PNP' - * devices on a legacy ISA/LPC bus. There is no need of probing of any kind, - * the only thing we have to do is to walk through the bus and + * and is specified in the config file. Typical examples are the 'PNP' + * devices on a legacy ISA/LPC bus. There is no need of probing of any kind, + * the only thing we have to do is to walk through the bus and * enable or disable devices as indicated in the config file. * * On the other hand, some devices are virtual and their existence is @@ -93,7 +93,7 @@ unsigned int scan_static_bus(device_t bus, unsigned int max) child->ops->enable(child); } if (child->path.type == DEVICE_PATH_I2C) { - printk(BIOS_DEBUG, "smbus: %s[%d]->", + printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(child->bus->dev), child->bus->link ); } printk(BIOS_DEBUG, "%s %s\n", diff --git a/src/drivers/ati/ragexl/atyfb.h b/src/drivers/ati/ragexl/atyfb.h index 3d9a8c5aa1..99a87b3371 100644 --- a/src/drivers/ati/ragexl/atyfb.h +++ b/src/drivers/ati/ragexl/atyfb.h @@ -1,7 +1,7 @@ /* * ATI Frame Buffer Device Driver Core Definitions */ - + #define PLL_CRTC_DECODE 0 #define EINVAL -1 diff --git a/src/drivers/ati/ragexl/fb.h b/src/drivers/ati/ragexl/fb.h index 01f2887707..48d0f0172f 100644 --- a/src/drivers/ati/ragexl/fb.h +++ b/src/drivers/ati/ragexl/fb.h @@ -119,7 +119,7 @@ struct fb_fix_screeninfo { u32 smem_len; /* Length of frame buffer mem */ u32 type; /* see FB_TYPE_* */ u32 type_aux; /* Interleave for interleaved Planes */ - u32 visual; /* see FB_VISUAL_* */ + u32 visual; /* see FB_VISUAL_* */ u16 xpanstep; /* zero if no hardware panning */ u16 ypanstep; /* zero if no hardware panning */ u16 ywrapstep; /* zero if no hardware ywrap */ @@ -142,8 +142,8 @@ struct fb_fix_screeninfo { struct fb_bitfield { u32 offset; /* beginning of bitfield */ u32 length; /* length of bitfield */ - u32 msb_right; /* != 0 : Most significant bit is */ - /* right */ + u32 msb_right; /* != 0 : Most significant bit is */ + /* right */ }; #define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ @@ -191,7 +191,7 @@ struct fb_var_screeninfo { struct fb_bitfield red; /* bitfield in fb mem if true color, */ struct fb_bitfield green; /* else only length is significant */ struct fb_bitfield blue; - struct fb_bitfield transp; /* transparency */ + struct fb_bitfield transp; /* transparency */ u32 nonstd; /* != 0 Non standard pixel format */ @@ -326,7 +326,7 @@ struct fb_info { devfs_handle_t devfs_handle; /* Devfs handle for new name */ devfs_handle_t devfs_lhandle; /* Devfs handle for compat. symlink */ int (*changevar)(int); /* tell console var has changed */ - int (*switch_con)(int, struct fb_info*); + int (*switch_con)(int, struct fb_info*); /* tell fb to switch consoles */ int (*updatevar)(int, struct fb_info*); /* tell fb to update the vars */ @@ -338,7 +338,7 @@ struct fb_info { the cursor's color for non palette mode */ /* From here on everything is device dependent */ - void *par; -}; + void *par; +}; #endif /* _LINUX_FB_H */ diff --git a/src/drivers/ati/ragexl/fbcon.h b/src/drivers/ati/ragexl/fbcon.h index 974e373215..d6f122cbb0 100644 --- a/src/drivers/ati/ragexl/fbcon.h +++ b/src/drivers/ati/ragexl/fbcon.h @@ -16,7 +16,7 @@ struct display { struct fb_var_screeninfo var; /* variable infos. yoffset and vmode */ /* are updated by fbcon.c */ struct fb_cmap cmap; /* colormap */ - char *screen_base; /* pointer to top of virtual screen */ + char *screen_base; /* pointer to top of virtual screen */ /* (virtual address) */ int visual; int type; /* see FB_TYPE_* */ @@ -96,11 +96,11 @@ struct display { ((s) & 0x400) #define attr_blink(p,s) \ ((s) & 0x8000) - + /* * Scroll Method */ - + /* Internal flags */ #define __SCROLL_YPAN 0x001 #define __SCROLL_YWRAP 0x002 diff --git a/src/drivers/ati/ragexl/mach64.h b/src/drivers/ati/ragexl/mach64.h index c3afff28aa..e0dae0df28 100644 --- a/src/drivers/ati/ragexl/mach64.h +++ b/src/drivers/ati/ragexl/mach64.h @@ -5,7 +5,7 @@ * written with much help from Jon Howell * * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven - * + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version diff --git a/src/drivers/ati/ragexl/mach64_ct.c b/src/drivers/ati/ragexl/mach64_ct.c index ca5283de27..b34be821fb 100644 --- a/src/drivers/ati/ragexl/mach64_ct.c +++ b/src/drivers/ati/ragexl/mach64_ct.c @@ -5,7 +5,7 @@ #if 0 #define FAIL(x) do { printk(BIOS_DEBUG, x); return -EINVAL; } while (0) #else -#define FAIL(x) +#define FAIL(x) #endif static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per, @@ -34,7 +34,7 @@ static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp, #if DEBUG_PLL==1 printk(BIOS_DEBUG, "aty_dsp_gt : mclk_fb_mult=%d\n", pll->mclk_fb_mult); #endif - + /* (64*xclk/vclk/bpp)<<11 = xclocks_per_row<<11 */ xclks_per_row = ((u32)pll->mclk_fb_mult * (u32)pll->mclk_fb_div * (u32)pll->vclk_post_div_real * 64) << 11; @@ -98,11 +98,11 @@ static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp, t_rp = ((memcntl >> 8) & 0x03) + 1; t_ras = ((memcntl >> 16) & 0x07) + 1; t_lat = (memcntl >> 4) & 0x03; - + t_pfc = t_rp + t_rcd + t_crd; t_rcc = max(t_rp + t_ras, t_pfc + n); - + /* fifo_on<<6 */ fifo_on = (2 * t_rcc + t_pfc + n - 1) << 6; @@ -125,9 +125,9 @@ static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per, int pllmclk, pllsclk; #endif u32 q; - + pll->pll_ref_div = info->pll_per*2*255/info->ref_clk_per; - + /* FIXME: use the VTB/GTB /3 post divider if it's better suited */ /* actually 8*q */ @@ -145,14 +145,14 @@ static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per, pll->mclk_post_div_real = 1; pll->sclk_fb_div = q*pll->mclk_post_div_real/8; -#if DEBUG_PLL==1 +#if DEBUG_PLL==1 pllsclk = (1000000 * 2 * pll->sclk_fb_div) / (info->ref_clk_per * pll->pll_ref_div); printk(BIOS_DEBUG, "aty_valid_pll_ct: pllsclk=%d MHz, mclk=%d MHz\n", pllsclk, pllsclk / pll->mclk_post_div_real); #endif - + pll->mclk_fb_mult = M64_HAS(MFB_TIMES_4) ? 4 : 2; /* actually 8*q */ @@ -177,7 +177,7 @@ static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per, printk(BIOS_DEBUG, "aty_valid_pll_ct: pllmclk=%d MHz, xclk=%d MHz\n", pllmclk, pllmclk / pll->xclk_post_div_real); #endif - + /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */ q = info->ref_clk_per*pll->pll_ref_div*4/vclk_per; /* actually 8*q */ if (q < 16*8 || q > 255*8) @@ -199,7 +199,7 @@ static void aty_calc_pll_ct(const struct fb_info_aty *info, struct pll_ct *pll) u8 xpostdiv = 0; u8 mpostdiv = 0; u8 vpostdiv = 0; - + if (M64_HAS(SDRAM_MAGIC_PLL) && (info->ram_type >= SDRAM)) pll->pll_gen_cntl = 0x64; /* mclk = sclk */ else @@ -221,7 +221,7 @@ static void aty_calc_pll_ct(const struct fb_info_aty *info, struct pll_ct *pll) } pll->spll_cntl2 = mpostdiv << 4; /* sclk == pllsclk / mpostdiv */ - + switch (pll->xclk_post_div_real) { case 1: xpostdiv = 0; @@ -316,12 +316,12 @@ void aty_set_pll_ct(const struct fb_info_aty *info, const union aty_pll *pll) aty_st_pll(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, info); aty_st_pll(MCLK_FB_DIV, pll->ct.mclk_fb_div, info); // for XCLK - + aty_st_pll(SPLL_CNTL2, pll->ct.spll_cntl2, info); aty_st_pll(SCLK_FB_DIV, pll->ct.sclk_fb_div, info); // for MCLK aty_st_pll(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, info); - + aty_st_pll(EXT_VPLL_CNTL, 0, info); aty_st_pll(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, info); aty_st_pll(VCLK_POST_DIV, pll->ct.vclk_post_div, info); diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index d776c26a78..8b02239833 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -96,7 +96,7 @@ static const struct xl_card_cfg_t { 0x10, 0x19 } }; - + typedef struct { u8 lcd_reg; u32 val; @@ -202,7 +202,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) u32 temp; union aty_pll pll; const struct xl_card_cfg_t * card = &card_cfg[xl_card]; - + aty_st_8(CONFIG_STAT0, 0x85, info); mdelay(10); @@ -222,7 +222,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) info->features &= ~M64F_MFB_TIMES_4; } #endif - + /* * Calculate mclk and xclk dividers, etc. The passed * pixclock and bpp values don't matter yet, the vclk @@ -243,7 +243,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, info); aty_st_pll(SPLL_CNTL2, 0x03, info); aty_st_pll(PLL_GEN_CNTL, 0x44, info); - + reset_clocks(info, &pll.ct, 0); mdelay(10); @@ -302,7 +302,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) aty_st_8(LCD_INDEX, 0x08, info); aty_st_8(LCD_DATA, 0x0B, info); mdelay(2); - + // enable display requests, enable CRTC aty_st_8(CRTC_GEN_CNTL+3, 0x02, info); // disable display @@ -482,7 +482,7 @@ static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk) info->mem_refresh_rate = i; } #endif /*CONFIG_CONSOLE_BTEXT */ -static void ati_ragexl_init(device_t dev) +static void ati_ragexl_init(device_t dev) { u32 chip_id; int j; @@ -513,9 +513,9 @@ static void ati_ragexl_init(device_t dev) #endif /*CONFIG_CONSOLE_BTEXT==1 */ struct fb_info_aty *info; - struct fb_info_aty info_t; - struct resource *res; - info = &info_t; + struct fb_info_aty info_t; + struct resource *res; + info = &info_t; #define USE_AUX_REG 1 @@ -529,12 +529,12 @@ static void ati_ragexl_init(device_t dev) info->frame_buffer = res->base; #endif /* CONFIG_CONSOLE_BTEXT */ -#if USE_AUX_REG==0 +#if USE_AUX_REG==0 info->ati_regbase = res->base+0x7ff000+0xc00; -#else +#else res = &dev->resource[2]; if(res->flags & IORESOURCE_MEM) { - info->ati_regbase = res->base+0x400; //using auxiliary register + info->ati_regbase = res->base+0x400; //using auxiliary register } #endif @@ -570,7 +570,7 @@ found: /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */ if (mclk == 67 && info->ram_type < SDRAM) mclk = 63; - } + } #endif #if CONFIG_CONSOLE_BTEXT==1 aty_calc_mem_refresh(info, type, xclk); @@ -583,14 +583,14 @@ found: // info->dac_ops = &aty_dac_ct; // info->pll_ops = &aty_pll_ct; info->bus_type = PCI; - + atyfb_xl_init(info); #if CONFIG_CONSOLE_BTEXT==1 info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07); - + info->ref_clk_per = 1000000000000ULL/14318180; xtal = "14.31818"; #if 0 @@ -719,7 +719,7 @@ found: } if (atyfb_decode_var(&var, &info->default_par, info)) { -#if 0 +#if 0 printk(BIOS_DEBUG, "atyfb: can't set default video mode\n"); #endif return ; @@ -779,7 +779,7 @@ found: #endif btext_clearscreen(); - + map_boot_text(); #if 0 @@ -791,7 +791,7 @@ found: #endif #endif /* CONFIG_CONSOLE_BTEXT */ - + } #if CONFIG_CONSOLE_BTEXT==1 @@ -856,13 +856,13 @@ static void aty_set_crtc(const struct fb_info_aty *info, static int aty_var_to_crtc(const struct fb_info_aty *info, const struct fb_var_screeninfo *var, struct crtc *crtc) -{ +{ u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp; u32 left, right, upper, lower, hslen, vslen, sync, vmode; u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; u32 pix_width, dp_pix_width, dp_chain_mask; - + /* input */ xres = var->xres; yres = var->yres; @@ -877,9 +877,9 @@ static int aty_var_to_crtc(const struct fb_info_aty *info, lower = var->lower_margin; hslen = var->hsync_len; vslen = var->vsync_len; - sync = var->sync; + sync = var->sync; vmode = var->vmode; - + /* convert (and round up) and validate */ xres = (xres+7) & ~7; xoffset = (xoffset+7) & ~7; @@ -887,7 +887,7 @@ static int aty_var_to_crtc(const struct fb_info_aty *info, if (vxres < xres+xoffset) vxres = xres+xoffset; h_disp = xres/8-1; - if (h_disp > 0xff) + if (h_disp > 0xff) FAIL("h_disp too large"); h_sync_strt = h_disp+(right/8); if (h_sync_strt > 0x1ff) @@ -924,7 +924,7 @@ static int aty_var_to_crtc(const struct fb_info_aty *info, pix_width = CRTC_PIX_WIDTH_8BPP; dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB; dp_chain_mask = 0x8080; - } + } #if SUPPORT_8_BPP_ABOVE==1 else if (bpp <= 16) { bpp = 16; @@ -943,7 +943,7 @@ static int aty_var_to_crtc(const struct fb_info_aty *info, dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP | BYTE_ORDER_LSB_TO_MSB; dp_chain_mask = 0x8080; - } + } #endif else FAIL("invalid bpp"); @@ -1123,7 +1123,7 @@ static int encode_fix(struct fb_fix_screeninfo *fix, fix->smem_start = info->frame_buffer; fix->smem_len = (u32)info->total_vram; - /* + /* * Reg Block 0 (CT-compatible block) is at ati_regbase_phys * Reg Block 1 (multimedia extensions) is at ati_regbase_phys-0x400 */ @@ -1158,11 +1158,11 @@ static int encode_fix(struct fb_fix_screeninfo *fix, #endif /* * Set the User Defined Part of the Display - */ -#if PLL_CRTC_DECODE==1 + */ +#if PLL_CRTC_DECODE==1 static int atyfb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb) -{ +{ struct fb_info_aty *info = (struct fb_info_aty *)fb; struct atyfb_par par; #if 0 @@ -1171,8 +1171,8 @@ static int atyfb_set_var(struct fb_var_screeninfo *var, int con, #endif int err; int activate = var->activate; - -#if 0 + +#if 0 if (con >= 0) display = &fb_display[con]; else @@ -1180,13 +1180,13 @@ static int atyfb_set_var(struct fb_var_screeninfo *var, int con, #if 0 display = fb->disp; /* used during initialization */ #endif - + if ((err = atyfb_decode_var(var, &par, info))) return err; - + atyfb_encode_var(var, &par, (struct fb_info_aty *)info); - -#if 0 + +#if 0 printk(BIOS_INFO, "atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK); #endif @@ -1262,7 +1262,7 @@ static void atyfb_set_par(const struct atyfb_par *par, #if PLL_CRTC_DECODE==1 info->current_par = *par; -#endif +#endif if (info->blitter_may_be_busy) wait_for_idle(info); @@ -1344,7 +1344,7 @@ static void atyfb_set_par(const struct atyfb_par *par, } #if 0 -static u16 red2[] = { +static u16 red2[] = { 0x0000, 0xaaaa }; static u16 green2[] = { @@ -1356,14 +1356,14 @@ static u16 blue2[] = { static u16 red4[] = { 0x0000, 0xaaaa, 0x5555, 0xffff -}; +}; static u16 green4[] = { 0x0000, 0xaaaa, 0x5555, 0xffff -}; +}; static u16 blue4[] = { 0x0000, 0xaaaa, 0x5555, 0xffff -}; - +}; + static u16 red8[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; @@ -1405,12 +1405,12 @@ static struct fb_cmap default_16_colors = { static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, u_int transp, struct fb_info_aty *info) -{ +{ int i, scale; - + if (regno > 255) return 1; - red >>= 8; + red >>= 8; green >>= 8; blue >>= 8; #if 0 @@ -1418,7 +1418,7 @@ static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, info->palette[regno].red = red; info->palette[regno].green = green; info->palette[regno].blue = blue; -#endif +#endif i = aty_ld_8(DAC_CNTL, info) & 0xfc; if (M64_HAS(EXTRA_BRIGHT)) i |= 0x2; /*DAC_CNTL|0x2 turns off the extra brightness for gt*/ @@ -1440,11 +1440,11 @@ int fb_set_cmap(struct fb_cmap *cmap, int kspc, int (*setcolreg)(u_int, u_int, u_int, u_int, u_int, struct fb_info_aty *), struct fb_info_aty *info) -{ +{ int i, start; u16 *red, *green, *blue, *transp; u_int hred, hgreen, hblue, htransp; - + red = cmap->red; green = cmap->green; blue = cmap->blue; @@ -1480,13 +1480,13 @@ struct fb_cmap *fb_default_cmap(int len) return &default_8_colors; #endif return &default_16_colors; -} +} static void do_install_cmap(int con, struct fb_info_aty *info) { #if PLL_CRTC_DECODE==1 int size = info->current_par.crtc.bpp == 16 ? 32 : 256; -#else +#else int size = 256; #endif fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info); diff --git a/src/drivers/emulation/qemu/fb.h b/src/drivers/emulation/qemu/fb.h index 01f2887707..48d0f0172f 100644 --- a/src/drivers/emulation/qemu/fb.h +++ b/src/drivers/emulation/qemu/fb.h @@ -119,7 +119,7 @@ struct fb_fix_screeninfo { u32 smem_len; /* Length of frame buffer mem */ u32 type; /* see FB_TYPE_* */ u32 type_aux; /* Interleave for interleaved Planes */ - u32 visual; /* see FB_VISUAL_* */ + u32 visual; /* see FB_VISUAL_* */ u16 xpanstep; /* zero if no hardware panning */ u16 ypanstep; /* zero if no hardware panning */ u16 ywrapstep; /* zero if no hardware ywrap */ @@ -142,8 +142,8 @@ struct fb_fix_screeninfo { struct fb_bitfield { u32 offset; /* beginning of bitfield */ u32 length; /* length of bitfield */ - u32 msb_right; /* != 0 : Most significant bit is */ - /* right */ + u32 msb_right; /* != 0 : Most significant bit is */ + /* right */ }; #define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ @@ -191,7 +191,7 @@ struct fb_var_screeninfo { struct fb_bitfield red; /* bitfield in fb mem if true color, */ struct fb_bitfield green; /* else only length is significant */ struct fb_bitfield blue; - struct fb_bitfield transp; /* transparency */ + struct fb_bitfield transp; /* transparency */ u32 nonstd; /* != 0 Non standard pixel format */ @@ -326,7 +326,7 @@ struct fb_info { devfs_handle_t devfs_handle; /* Devfs handle for new name */ devfs_handle_t devfs_lhandle; /* Devfs handle for compat. symlink */ int (*changevar)(int); /* tell console var has changed */ - int (*switch_con)(int, struct fb_info*); + int (*switch_con)(int, struct fb_info*); /* tell fb to switch consoles */ int (*updatevar)(int, struct fb_info*); /* tell fb to update the vars */ @@ -338,7 +338,7 @@ struct fb_info { the cursor's color for non palette mode */ /* From here on everything is device dependent */ - void *par; -}; + void *par; +}; #endif /* _LINUX_FB_H */ diff --git a/src/drivers/emulation/qemu/fbcon.h b/src/drivers/emulation/qemu/fbcon.h index 8b83a3682b..0656c6f462 100644 --- a/src/drivers/emulation/qemu/fbcon.h +++ b/src/drivers/emulation/qemu/fbcon.h @@ -19,7 +19,7 @@ struct display { struct fb_var_screeninfo var; /* variable infos. yoffset and vmode */ /* are updated by fbcon.c */ struct fb_cmap cmap; /* colormap */ - char *screen_base; /* pointer to top of virtual screen */ + char *screen_base; /* pointer to top of virtual screen */ /* (virtual address) */ int visual; int type; /* see FB_TYPE_* */ @@ -108,11 +108,11 @@ struct display { ((s) & 0x400) #define attr_blink(p,s) \ ((s) & 0x8000) - + /* * Scroll Method */ - + /* Internal flags */ #define __SCROLL_YPAN 0x001 #define __SCROLL_YWRAP 0x002 diff --git a/src/drivers/emulation/qemu/init.c b/src/drivers/emulation/qemu/init.c index 20e080b4f7..ae38d2b9ed 100644 --- a/src/drivers/emulation/qemu/init.c +++ b/src/drivers/emulation/qemu/init.c @@ -57,7 +57,7 @@ static void qemu_init(void) int width=640, height=480, depth=8; printk(BIOS_DEBUG, "Initializing VGA!\n"); - + vbe_outw(VBE_DISPI_INDEX_XRES, width); vbe_outw(VBE_DISPI_INDEX_YRES, height); vbe_outw(VBE_DISPI_INDEX_BPP, depth); diff --git a/src/drivers/generic/debug/debug_dev.c b/src/drivers/generic/debug/debug_dev.c index 6af5325926..5c5dc8b16e 100644 --- a/src/drivers/generic/debug/debug_dev.c +++ b/src/drivers/generic/debug/debug_dev.c @@ -16,7 +16,7 @@ static void print_pci_regs(struct device *dev) for(i=0;i<256;i++) { byte = pci_read_config8(dev, i); - + if((i & 0xf)==0) printk(BIOS_DEBUG, "\n%02x:",i); printk(BIOS_DEBUG, " %02x",byte); } @@ -51,7 +51,7 @@ static void print_pci_regs_all(void) if(!dev->enabled) { continue; } - printk(BIOS_DEBUG, "\n%02x:%02x:%02x aka %s", + printk(BIOS_DEBUG, "\n%02x:%02x:%02x aka %s", bus, device, function, dev_path(dev)); print_pci_regs(dev); } @@ -83,7 +83,7 @@ static void print_cpuid(void) } static void print_smbus_regs(struct device *dev) -{ +{ int j; printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link); printk(BIOS_DEBUG, "%s", dev_path(dev)); @@ -97,7 +97,7 @@ static void print_smbus_regs(struct device *dev) } if ((j & 0xf) == 0) { printk(BIOS_DEBUG, "\n%02x: ", j); - } + } byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } @@ -113,12 +113,12 @@ static void print_smbus_regs_all(struct device *dev) // Here don't need to call smbus_set_link, because we scan it from top to down if( dev->bus->dev->path.type == DEVICE_PATH_I2C) { // it's under i2c MUX so set mux at first if(ops_smbus_bus(get_pbus_smbus(dev->bus->dev))) { - if(dev->bus->dev->ops && dev->bus->dev->ops->set_link) + if(dev->bus->dev->ops && dev->bus->dev->ops->set_link) dev->bus->dev->ops->set_link(dev->bus->dev, dev->bus->link); } } - - if(ops_smbus_bus(get_pbus_smbus(dev))) print_smbus_regs(dev); + + if(ops_smbus_bus(get_pbus_smbus(dev))) print_smbus_regs(dev); } for(i=0; i< dev->links; i++) { @@ -142,7 +142,7 @@ static void print_msr_dualcore(void) printk(BIOS_DEBUG, "cpuid[%08x]: %08x %08x %08x %08x\n", index, eax, ebx, ecx, edx); - printk(BIOS_DEBUG, "core number %d\n", ecx & 0xff); + printk(BIOS_DEBUG, "core number %d\n", ecx & 0xff); index = 0xc001001f; printk(BIOS_DEBUG, "Reading msr: 0x%08x\n", index); @@ -217,7 +217,7 @@ static tsc_t rdtsc(void) } static void print_tsc(void) { - + tsc_t tsc; tsc = rdtsc(); printk(BIOS_DEBUG, "tsc: 0x%08x%08x\n", @@ -245,29 +245,29 @@ static void debug_init(device_t dev) printk(BIOS_DEBUG, "\n"); } break; - + case 1: print_pci_regs_all(); break; - case 2: + case 2: print_mem(); break; case 3: print_cpuid(); break; - case 4: + case 4: print_smbus_regs_all(&dev_root); break; - case 5: + case 5: print_msr_dualcore(); break; - case 6: + case 6: print_cache_size(); break; case 7: print_tsc(); break; - case 8: + case 8: hard_reset(); break; } @@ -291,5 +291,5 @@ static void enable_dev(struct device *dev) struct chip_operations drivers_generic_debug_ops = { CHIP_NAME("Debug device") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index 8cf6281bda..14b07aa90c 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -27,10 +27,10 @@ static void adm1026_init(device_t dev) if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if(ops_smbus_bus(get_pbus_smbus(dev))) { - if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux + if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux adm1026_enable_monitoring(dev); } - + } } @@ -65,5 +65,5 @@ static void enable_dev(struct device *dev) struct chip_operations drivers_i2c_adm1026_ops = { CHIP_NAME("adm1026") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c index 8329f08414..bca2c0dbc8 100644 --- a/src/drivers/i2c/adm1027/adm1027.c +++ b/src/drivers/i2c/adm1027/adm1027.c @@ -44,7 +44,7 @@ static void adm1027_init(device_t dev) if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { if (dev->bus->dev->path.type == DEVICE_PATH_I2C) - smbus_set_link(dev); // it is under mux + smbus_set_link(dev); // it is under mux adm1027_enable_monitoring(dev); } diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index 512b19f48a..cd68a01ebf 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -15,7 +15,7 @@ static void i2cmux_set_link(device_t dev, unsigned int link) smbus_write_byte(dev, 0x01, 1<enabled && dev->path.type == DEVICE_PATH_I2C) { if(ops_smbus_bus(get_pbus_smbus(dev))) { - if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux + if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux result = smbus_read_byte(dev, 0x03); // result &= ~0x04; result |= 0x04; smbus_write_byte(dev, 0x03, result & 0xff); // config lm63 } - + } } @@ -42,5 +42,5 @@ static void enable_dev(struct device *dev) struct chip_operations drivers_i2c_lm63_ops = { CHIP_NAME("National Semiconductor LM63") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/drivers/si/3114/si_sata.c b/src/drivers/si/3114/si_sata.c index 8d06fb6fbc..6661c2046d 100644 --- a/src/drivers/si/3114/si_sata.c +++ b/src/drivers/si/3114/si_sata.c @@ -29,10 +29,10 @@ static void si_sata_init(struct device *dev) /* some driver change class code to 0x104, but not change deviceid without reason*/ /* restore it so we don't need to unplug AC power to restore it*/ - + word = pci_read_config16(dev, 0x0a); if(word!=0x0180) { - /* enble change device id and class id*/ + /* enble change device id and class id*/ dword = pci_read_config32(dev,0x40); dword |= (1<<0); pci_write_config32(dev, 0x40, dword); @@ -49,7 +49,7 @@ static void si_sata_init(struct device *dev) } - + } static struct device_operations si_sata_ops = { .read_resources = pci_dev_read_resources, @@ -64,4 +64,4 @@ static const struct pci_driver si_sata_driver __pci_driver = { .vendor = 0x1095, .device = 0x3114, }; - + diff --git a/src/drivers/trident/blade3d/blade3d.c b/src/drivers/trident/blade3d/blade3d.c index e50d40514b..1d79766b9c 100644 --- a/src/drivers/trident/blade3d/blade3d.c +++ b/src/drivers/trident/blade3d/blade3d.c @@ -65,7 +65,7 @@ typedef struct Reg_struct { BYTE rMask; } Def_Reg_struct; -typedef Def_Reg_struct* lpDef_Reg_struct; +typedef Def_Reg_struct* lpDef_Reg_struct; // , *pDef_Reg_struct, far * lpDef_Reg_struct; static Def_Reg_struct Mode3_temp[] = { //mode3 temp @@ -209,7 +209,7 @@ static Def_Reg_struct Init_reg[] = { {Port_GRX, 0x33, 0x20, 0x00}, {Port_GRX, 0x30, 0x00, 0x00}, // - {Port_GRX, 0x28, 0x18, 0x00}, + {Port_GRX, 0x28, 0x18, 0x00}, {Port_CRX, 0x0F, 0x20, 0x40}, {Port_CRX, 0x1F, 0x00, 0x00}, @@ -806,7 +806,7 @@ static void config_OEM_regs(void) lpInit_reg = &Init_reg[0]; printk(BIOS_DEBUG, "blade3d: config_OEM_regs()\n"); - + outp(Port_GRX, 0x24); outp(Port_GRX + 1, 0xe0); //MCLK VCLK to 16 bit @@ -1025,4 +1025,4 @@ static const struct pci_driver trident_blade3d_driver __pci_driver = { .vendor = 0x1023, .device = 0x9880, }; - + diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index cec394e474..19d2881f43 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -33,7 +33,7 @@ /* Since coreboot is usually compiled 32bit, gcc will align 64bit * types to 32bit boundaries. If the coreboot table is dumped on a - * 64bit system, a uint64_t would be aligned to 64bit boundaries, + * 64bit system, a uint64_t would be aligned to 64bit boundaries, * breaking the table format. * * lb_uint64 will keep 64bit coreboot table values aligned to 32bit @@ -216,7 +216,7 @@ struct cmos_entries { uint32_t config; /* e=enumeration, h=hex, r=reserved */ uint32_t config_id; /* a number linking to an enumeration record */ #define CMOS_MAX_NAME_LENGTH 32 - uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii, + uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii, variable length int aligned */ }; @@ -232,7 +232,7 @@ struct cmos_enums { uint32_t config_id; /* a number identifying the config id */ uint32_t value; /* the value associated with the text */ #define CMOS_MAX_TEXT_LENGTH 32 - uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii, + uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii, variable length int aligned */ }; diff --git a/src/include/boot/elf_boot.h b/src/include/boot/elf_boot.h index ee6750d293..b119babc00 100644 --- a/src/include/boot/elf_boot.h +++ b/src/include/boot/elf_boot.h @@ -1,5 +1,5 @@ -#ifndef ELF_BOOT_H -#define ELF_BOOT_H +#ifndef ELF_BOOT_H +#define ELF_BOOT_H #include @@ -32,7 +32,7 @@ typedef struct Elf_Half b_records; } Elf_Bhdr; -typedef struct +typedef struct { Elf_Word n_namesz; /* Length of the note's name. */ Elf_Word n_descsz; /* Length of the note's descriptor. */ diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 6eb706284c..c17d13f64f 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -84,7 +84,7 @@ struct cbfs_header { u32 magic; - u32 version; + u32 version; u32 romsize; u32 bootblocksize; u32 align; diff --git a/src/include/console/btext.h b/src/include/console/btext.h index 88d93931b9..1d2e37e1fc 100644 --- a/src/include/console/btext.h +++ b/src/include/console/btext.h @@ -3,7 +3,7 @@ * (for MacOS) when it is used to boot Linux. * * Written by Benjamin Herrenschmidt. - * + * * Move to coreboot by LYH yhlu@tyan.com * */ diff --git a/src/include/console/console.h b/src/include/console/console.h index be91988291..36661c25c7 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -30,7 +30,7 @@ extern struct console_driver econsole_drivers[]; extern int console_loglevel; #else /* __PRE_RAM__ */ -/* Using a global varible can cause problems when we reset the stack +/* Using a global varible can cause problems when we reset the stack * from cache as ram to ram. If we make this a define USE_SHARED_STACK * we could use the same code on all architectures. */ diff --git a/src/include/console/vtxprintf.h b/src/include/console/vtxprintf.h index f7d58bbd6a..2cf44de7ea 100644 --- a/src/include/console/vtxprintf.h +++ b/src/include/console/vtxprintf.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/include/cpu/amd/amdk8_sysconf.h b/src/include/cpu/amd/amdk8_sysconf.h index 28158a6c38..3ae35fd17d 100644 --- a/src/include/cpu/amd/amdk8_sysconf.h +++ b/src/include/cpu/amd/amdk8_sysconf.h @@ -20,7 +20,7 @@ struct amdk8_sysconf_t { int apicid_offset; void *mb; // pointer for mb releated struct - + }; extern struct amdk8_sysconf_t sysconf; diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index ec99b95395..681b90cca0 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -284,20 +284,20 @@ #define SMM_INST_EN_SET (1<<3) #define INTL_SMI_EN_SET (1<<4) #define EXTL_SMI_EN_SET (1<<5) - + #define CPU_FPU_MSR_MODE 0x1A00 #define FPU_IE_SET (1<<0) - + #define CPU_FP_UROM_BIST 0x1A03 - + #define CPU_BC_CONF_0 0x1900 #define TSC_SUSP_SET (1<<5) #define SUSP_EN_SET (1<<12) - + /**/ /* VG GLIU0 port4*/ /**/ - + #define VG_GLD_MSR_CAP (MSR_VG + 0x2000) #define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001) #define VG_GLD_MSR_PM (MSR_VG + 0x2004) @@ -332,7 +332,7 @@ #define RSTPLL_UPPER_MDIV_SHIFT 9 #define RSTPLL_UPPER_VDIV_SHIFT 6 #define RSTPLL_UPPER_FBDIV_SHIFT 0 - + #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 #define RSTPLL_LOWER_SWFLAGS_MASK (0x3F< 720x480p // MED -> 1280x720p // HI -> 1920x1080i - // FS454 - Both SD and HD resolutions + // FS454 - Both SD and HD resolutions // SD Resolutions - NTSC and PAL // LO -> 640x480 // MED -> 800x600 @@ -331,8 +331,8 @@ #define RW_PIRQ 0x06 // read/write PCI IRQ router regs in SB Func0 cfg space #define SLPB_CLEAR 0x07 // clear sleep button GPIO status's #define PIRQ_ROUTING 0x08 // read the PCI IRQ routing based on BIOS setup - #define ACPI_UNUSED2 0x09 - #define ACPI_UNUSED3 0x0A + #define ACPI_UNUSED2 0x09 + #define ACPI_UNUSED3 0x0A #define PIC_INTERRUPT 0x0B #define ACPI_PRESENT 0x0C #define ACPI_GEN_COMMAND 0x0D @@ -380,7 +380,7 @@ #define VRC_DEBUGGER 0x0E #define MAX_DEBUGGER NO_VR - + #define VRC_STR 0x0F // Virtual Register class #define RESTORE_ADDR 0x00 // Physical address of MSR restore table @@ -404,7 +404,7 @@ #define VRC_SYSINFO 0x12 // Virtual Register class #define VRC_SI_VERSION 0x00 // Sysinfo VSM version - #define VRC_SI_CPU_MHZ 0x01 // CPU speed in MHZ + #define VRC_SI_CPU_MHZ 0x01 // CPU speed in MHZ #define VRC_SI_CHIPSET_BASE_LOW 0x02 #define VRC_SI_CHIPSET_BASE_HI 0x03 #define VRC_SI_CHIPSET_ID 0x04 diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index be27f1d9ea..f3ac2ed11f 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2004 Eric W. Biederman * * This program is free software; you can redistribute it and/or modify diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index cbbd5cfd85..daa7e18422 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -17,7 +17,7 @@ static void wrmsr(unsigned long index, msr_t msr) #else -typedef struct msr_struct +typedef struct msr_struct { unsigned lo; unsigned hi; diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index c1eb022886..eb8fa5a91c 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -1,5 +1,5 @@ #ifndef CPU_X86_PAE_H -#define CPU_X86_PAE_H +#define CPU_X86_PAE_H #define MAPPING_ERROR ((void *)0xffffffffUL) void *map_2M_page(unsigned long page); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 2954ecd1f7..155f666b3c 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* AMD64 SMM State-Save Area +/* AMD64 SMM State-Save Area * starts @ 0x7e00 */ typedef struct { @@ -115,7 +115,7 @@ typedef struct { } __attribute__((packed)) amd64_smm_state_save_area_t; -/* Intel Core 2 (EM64T) SMM State-Save Area +/* Intel Core 2 (EM64T) SMM State-Save Area * starts @ 0x7d00 */ typedef struct { @@ -193,7 +193,7 @@ typedef struct { } __attribute__((packed)) em64t_smm_state_save_area_t; -/* Legacy x86 SMM State-Save Area +/* Legacy x86 SMM State-Save Area * starts @ 0x7e00 */ diff --git a/src/include/cpu/x86/stack.h b/src/include/cpu/x86/stack.h index d39764a7d6..158b670251 100644 --- a/src/include/cpu/x86/stack.h +++ b/src/include/cpu/x86/stack.h @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify diff --git a/src/include/device/agp.h b/src/include/device/agp.h index 073858ae10..564b0bb4e6 100644 --- a/src/include/device/agp.h +++ b/src/include/device/agp.h @@ -2,7 +2,7 @@ #define DEVICE_AGP_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int agp_scan_bus(struct bus *bus, +unsigned int agp_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); unsigned int agp_scan_bridge(device_t dev, unsigned int max); diff --git a/src/include/device/cardbus.h b/src/include/device/cardbus.h index 07cc46a54a..5b003d3217 100644 --- a/src/include/device/cardbus.h +++ b/src/include/device/cardbus.h @@ -3,7 +3,7 @@ /* (c) 2005 Linux Networx GPL see COPYING for details */ void cardbus_read_resources(device_t dev); -unsigned int cardbus_scan_bus(struct bus *bus, +unsigned int cardbus_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); unsigned int cardbus_scan_bridge(device_t dev, unsigned int max); void cardbus_enable_resources(device_t dev); diff --git a/src/include/device/device.h b/src/include/device/device.h index df8fb5f6d5..59dd0815e6 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -49,8 +49,8 @@ struct bus { unsigned disable_relaxed_ordering : 1; }; -#define MAX_RESOURCES 24 -#define MAX_LINKS 8 +#define MAX_RESOURCES 24 +#define MAX_LINKS 8 /* * There is one device structure for each slot-number/function-number * combination: @@ -78,7 +78,7 @@ struct device { unsigned int resources; /* links are (downstream) buses attached to the device, usually a leaf - * device with no children have 0 buses attached and a bridge has 1 bus + * device with no children have 0 buses attached and a bridge has 1 bus */ struct bus link[MAX_LINKS]; /* number of buses attached to the device */ @@ -139,10 +139,10 @@ void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char* msg); -/* Rounding for boundaries. +/* Rounding for boundaries. * Due to some chip bugs, go ahead and round IO to 16 */ -#define DEVICE_IO_ALIGN 16 +#define DEVICE_IO_ALIGN 16 #define DEVICE_MEM_ALIGN 4096 extern struct device_operations default_dev_ops_root; diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h index 6a350f8232..e927d617fd 100644 --- a/src/include/device/hypertransport.h +++ b/src/include/device/hypertransport.h @@ -3,7 +3,7 @@ #include -unsigned int hypertransport_scan_chain(struct bus *bus, +unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unit_base, unsigned offset_unitid); unsigned int ht_scan_bridge(struct device *dev, unsigned int max); extern struct device_operations default_ht_ops_bus; diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h index 6c12dcf39f..d6276ba003 100644 --- a/src/include/device/hypertransport_def.h +++ b/src/include/device/hypertransport_def.h @@ -11,7 +11,7 @@ #define HT_FREQ_1200Mhz 7 #define HT_FREQ_1400Mhz 8 #define HT_FREQ_1600Mhz 9 -#define HT_FREQ_1800Mhz 10 +#define HT_FREQ_1800Mhz 10 #define HT_FREQ_2000Mhz 11 #define HT_FREQ_2200Mhz 12 #define HT_FREQ_2400Mhz 13 diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 5485644393..131564c8c5 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -61,7 +61,7 @@ void pci_bus_enable_resources(device_t dev); void pci_bus_reset(struct bus *bus); device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn); unsigned int do_pci_scan_bridge(device_t bus, unsigned int max, - unsigned int (*do_scan_bus)(struct bus *bus, + unsigned int (*do_scan_bus)(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max)); unsigned int pci_scan_bridge(device_t bus, unsigned int max); unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index ba972547ea..a5aa3a1c3b 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -26,7 +26,7 @@ #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ -#define PCI_STATUS_DEVSEL_FAST 0x000 +#define PCI_STATUS_DEVSEL_FAST 0x000 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 #define PCI_STATUS_DEVSEL_SLOW 0x400 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ @@ -55,8 +55,8 @@ /* * Base addresses specify locations in memory or I/O space. - * Decoded size can be determined by writing a value of - * 0xffffffff to the register, and reading it back. Only + * Decoded size can be determined by writing a value of + * 0xffffffff to the register, and reading it back. Only * 1 bits are decoded. */ #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ @@ -80,7 +80,7 @@ /* Header type 0 (normal devices) */ #define PCI_CARDBUS_CIS 0x28 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c -#define PCI_SUBSYSTEM_ID 0x2e +#define PCI_SUBSYSTEM_ID 0x2e #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ #define PCI_ROM_ADDRESS_ENABLE 0x01 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) @@ -189,7 +189,7 @@ /* Hypertransport Registers */ #define PCI_HT_CAP_SIZEOF 4 -#define PCI_HT_CAP_HOST_CTRL 4 /* Host link control */ +#define PCI_HT_CAP_HOST_CTRL 4 /* Host link control */ #define PCI_HT_CAP_HOST_WIDTH 6 /* width value & capability */ #define PCI_HT_CAP_HOST_FREQ 0x09 /* Host frequency */ #define PCI_HT_CAP_HOST_FREQ_CAP 0x0a /* Host Frequency capability */ diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 9ea662d490..becc800934 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -2,7 +2,7 @@ #define DEVICE_PCIEXP_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int pciexp_scan_bus(struct bus *bus, +unsigned int pciexp_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index 8bf193530a..e017922ef1 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -2,7 +2,7 @@ #define DEVICE_PCIX_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int pcix_scan_bus(struct bus *bus, +unsigned int pcix_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); unsigned int pcix_scan_bridge(device_t dev, unsigned int max); const char *pcix_speed(unsigned sstatus); diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h index 09a77e72f1..8da08a2250 100644 --- a/src/include/smp/atomic.h +++ b/src/include/smp/atomic.h @@ -11,40 +11,40 @@ typedef struct { int counter; } atomic_t; /** * atomic_read - read atomic variable * @v: pointer of type atomic_t - * + * * Atomically reads the value of @v. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_read(v) ((v)->counter) /** * atomic_set - set atomic variable * @v: pointer of type atomic_t * @i: required value - * + * * Atomically sets the value of @v to @i. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_set(v,i) (((v)->counter) = (i)) /** * atomic_inc - increment atomic variable * @v: pointer of type atomic_t - * + * * Atomically increments @v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_inc(v) (((v)->counter)++) /** * atomic_dec - decrement atomic variable * @v: pointer of type atomic_t - * + * * Atomically decrements @v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. - */ + */ #define atomic_dec(v) (((v)->counter)--) diff --git a/src/include/string.h b/src/include/string.h index b4edf432ac..04c3733f8b 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -12,10 +12,10 @@ int memcmp(const void *s1, const void *s2, size_t n); int sprintf(char * buf, const char *fmt, ...); #endif -// simple string functions +// simple string functions -static inline size_t strnlen(const char *src, size_t max) -{ +static inline size_t strnlen(const char *src, size_t max) +{ size_t i = 0; while((*src++) && (i < max)) { i++; @@ -37,13 +37,13 @@ static inline char *strchr(const char *s, int c) for (; *s; s++) { if (*s == c) return (char *) s; - } + } return 0; } #if !defined(__PRE_RAM__) static inline char *strdup(const char *s) -{ +{ size_t sz = strlen(s) + 1; char *d = malloc(sz); memcpy(d, s, sz); @@ -69,7 +69,7 @@ static inline char *strncpy(char *to, const char *from, int count) } static inline int strcmp(const char *s1, const char *s2) -{ +{ int r; while ((r = (*s1 - *s2)) == 0 && *s1) { @@ -77,7 +77,7 @@ static inline int strcmp(const char *s1, const char *s2) s2++; } return r; -} +} static inline int strncmp(const char *s1, const char *s2, int maxlen) { diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 390e7796e8..690033e6b0 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -160,11 +160,11 @@ void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest) if (orom == NULL) return NULL; - /* They might have specified a dest address. If so, we can decompress. + /* They might have specified a dest address. If so, we can decompress. * If not, there's not much hope of decompressing or relocating the rom. * in the common case, the expansion rom is uncompressed, we - * pass 0 in for the dest, and all we have to do is find the rom and - * return a pointer to it. + * pass 0 in for the dest, and all we have to do is find the rom and + * return a pointer to it. */ /* BUG: the cbfstool is (not yet) including a cbfs_optionrom header */ @@ -193,9 +193,9 @@ void * cbfs_load_stage(const char *name) if (stage == NULL) return (void *) -1; - printk(BIOS_INFO, "Stage: loading %s @ 0x%x (%d bytes), entry @ 0x%llx\n", + printk(BIOS_INFO, "Stage: loading %s @ 0x%x (%d bytes), entry @ 0x%llx\n", name, - (u32) stage->load, stage->memlen, + (u32) stage->load, stage->memlen, stage->entry); memset((void *) (u32) stage->load, 0, stage->memlen); @@ -235,9 +235,9 @@ int cbfs_execute_stage(const char *name) /** * run_address is passed the address of a function taking no parameters and - * jumps to it, returning the result. - * @param f the address to call as a function. - * @return value returned by the function. + * jumps to it, returning the result. + * @param f the address to call as a function. + * @return value returned by the function. */ int run_address(void *f) diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 9e8aff3e67..7e3e20123a 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -67,7 +67,7 @@ void cbmem_init(u64 baseaddr, u64 size) #ifndef __PRE_RAM__ bss_cbmem_toc = cbmem_toc; #endif - + debug("Initializing CBMEM area to 0x%llx (%lld bytes)\n", baseaddr, size); if (size < (64 * 1024)) { @@ -103,7 +103,7 @@ void *cbmem_add(u32 id, u64 size) struct cbmem_entry *cbmem_toc; int i; cbmem_toc = get_cbmem_toc(); - + if (cbmem_toc == NULL) { return NULL; } @@ -121,7 +121,7 @@ void *cbmem_add(u32 id, u64 size) /* Align size to 512 byte blocks */ - size = ALIGN(size, 512) < cbmem_toc[0].size ? + size = ALIGN(size, 512) < cbmem_toc[0].size ? ALIGN(size, 512) : cbmem_toc[0].size; /* Now look for the first free/usable TOC entry */ @@ -155,7 +155,7 @@ void *cbmem_find(u32 id) struct cbmem_entry *cbmem_toc; int i; cbmem_toc = get_cbmem_toc(); - + if (cbmem_toc == NULL) return NULL; @@ -197,7 +197,7 @@ void cbmem_list(void) struct cbmem_entry *cbmem_toc; int i; cbmem_toc = get_cbmem_toc(); - + if (cbmem_toc == NULL) return; diff --git a/src/lib/compute_ip_checksum.c b/src/lib/compute_ip_checksum.c index 9306baf5d0..48f93d4699 100644 --- a/src/lib/compute_ip_checksum.c +++ b/src/lib/compute_ip_checksum.c @@ -39,7 +39,7 @@ unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned sum = ~sum & 0xFFFF; new = ~new & 0xFFFF; if (offset & 1) { - /* byte swap the sum if it came from an odd offset + /* byte swap the sum if it came from an odd offset * since the computation is endian independant this * works. */ diff --git a/src/lib/generic_dump_spd.c b/src/lib/generic_dump_spd.c index 2fe1ea305b..32a572e44c 100644 --- a/src/lib/generic_dump_spd.c +++ b/src/lib/generic_dump_spd.c @@ -12,8 +12,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -38,8 +38,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { diff --git a/src/lib/generic_sdram.c b/src/lib/generic_sdram.c index edecc06850..8a06252170 100644 --- a/src/lib/generic_sdram.c +++ b/src/lib/generic_sdram.c @@ -45,7 +45,7 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl) } /* Now that everything is setup enable the SDRAM. - * Some chipsets do the work for us while on others + * Some chipsets do the work for us while on others * we need to it by hand. */ print_debug("Ram3\n"); diff --git a/src/lib/jpeg.c b/src/lib/jpeg.c index 1e917c2b40..4297299ee5 100644 --- a/src/lib/jpeg.c +++ b/src/lib/jpeg.c @@ -270,7 +270,7 @@ int jpeg_check_size(unsigned char *buf, int width, int height) return 1; } -int jpeg_decode(unsigned char *buf, unsigned char *pic, +int jpeg_decode(unsigned char *buf, unsigned char *pic, int width, int height, int depth, struct jpeg_decdata *decdata) { int i, j, m, tac, tdc; diff --git a/src/lib/lzma.c b/src/lib/lzma.c index 532a2b2614..be0f386bdf 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -1,4 +1,4 @@ -/* +/* Coreboot interface to memory-saving variant of LZMA decoder diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index 65819b53cf..1cf647d27b 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -1,21 +1,21 @@ /* LzmaDecode.c LZMA Decoder (optimized for Speed version) - + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) http://www.7-zip.org/ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this Code, expressly permits you to - statically or dynamically link your Code (or bind by name) to the - interfaces of this file without subjecting your linked Code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ @@ -37,7 +37,7 @@ #define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } #define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - + #define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } @@ -47,9 +47,9 @@ #define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) #define RangeDecoderBitTreeDecode(probs, numLevels, res) \ { int i = numLevels; res = 1; \ @@ -72,7 +72,7 @@ #define LenLow (LenChoice2 + 1) #define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) #define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) #define kNumStates 12 @@ -161,7 +161,7 @@ int LzmaDecode(CLzmaDecoderState *vs, for (i = 0; i < numProbs; i++) p[i] = kBitModelTotal >> 1; } - + RC_INIT(inStream, inSize); @@ -170,7 +170,7 @@ int LzmaDecode(CLzmaDecoderState *vs, CProb *prob; UInt32 bound; int posState = (int)( - (nowPos + (nowPos ) & posStateMask); @@ -179,9 +179,9 @@ int LzmaDecode(CLzmaDecoderState *vs, { int symbol = 1; UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * + prob = p + Literal + (LZMA_LIT_SIZE * ((( - (nowPos + (nowPos ) & literalPosMask) << lc) + (previousByte >> (8 - lc)))); @@ -212,7 +212,7 @@ int LzmaDecode(CLzmaDecoderState *vs, else if (state < 10) state -= 3; else state -= 6; } - else + else { UpdateBit1(prob); prob = p + IsRep + state; @@ -236,10 +236,10 @@ int LzmaDecode(CLzmaDecoderState *vs, IfBit0(prob) { UpdateBit0(prob); - + if (nowPos == 0) return LZMA_RESULT_DATA_ERROR; - + state = state < kNumLitStates ? 9 : 11; previousByte = outStream[nowPos - rep0]; outStream[nowPos++] = previousByte; @@ -261,7 +261,7 @@ int LzmaDecode(CLzmaDecoderState *vs, UpdateBit0(prob); distance = rep1; } - else + else { UpdateBit1(prob); prob = p + IsRepG2 + state; @@ -322,7 +322,7 @@ int LzmaDecode(CLzmaDecoderState *vs, int posSlot; state += kNumLitStates; prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); if (posSlot >= kStartPosModelIndex) diff --git a/src/lib/lzmadecode.h b/src/lib/lzmadecode.h index dedde0de67..34c9f14c33 100644 --- a/src/lib/lzmadecode.h +++ b/src/lib/lzmadecode.h @@ -1,4 +1,4 @@ -/* +/* LzmaDecode.h LZMA Decoder interface @@ -8,14 +8,14 @@ LZMA SDK is licensed under two licenses: 1) GNU Lesser General Public License (GNU LGPL) 2) Common Public License (CPL) - It means that you can select one of these two licenses and + It means that you can select one of these two licenses and follow rules of that license. SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions to this file, however, are subject to the LGPL or CPL terms. */ diff --git a/src/lib/nrv2b.c b/src/lib/nrv2b.c index c91eda5047..d84e99ec0b 100644 --- a/src/lib/nrv2b.c +++ b/src/lib/nrv2b.c @@ -1,4 +1,4 @@ -// This GETBIT is supposed to work on little endian +// This GETBIT is supposed to work on little endian // 32bit systems. The algorithm will definitely need // some fixing on other systems, but it might not be // a problem since the nrv2b binary behaves the same.. @@ -37,7 +37,7 @@ static unsigned long unrv2b(uint8_t * src, uint8_t * dst, unsigned long *ilen_p) // skip length src += 4; - /* FIXME: check olen with the length stored in first 4 bytes */ + /* FIXME: check olen with the length stored in first 4 bytes */ for (;;) { unsigned int m_off, m_len; diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 605d555e46..98872a47d7 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -48,7 +48,7 @@ static void phys_memory_barrier(void) static void ram_fill(unsigned long start, unsigned long stop) { unsigned long addr; - /* + /* * Fill. */ #if CONFIG_USE_PRINTK_IN_CAR @@ -85,7 +85,7 @@ static void ram_verify(unsigned long start, unsigned long stop) { unsigned long addr; int i = 0; - /* + /* * Verify. */ #if CONFIG_USE_PRINTK_IN_CAR @@ -168,7 +168,7 @@ void ram_check(unsigned long start, unsigned long stop) #else print_debug("Testing DRAM : "); print_debug_hex32(start); - print_debug("-"); + print_debug("-"); print_debug_hex32(stop); print_debug("\n"); #endif diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 79eb1c51c1..3dbee0b464 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -33,7 +33,7 @@ static inline void uart8250_wait_to_tx_byte(unsigned base_port) static inline void uart8250_wait_until_sent(unsigned base_port) { - while(!(inb(base_port + UART_LSR) & 0x40)) + while(!(inb(base_port + UART_LSR) & 0x40)) ; } diff --git a/src/lib/usbdebug_direct.c b/src/lib/usbdebug_direct.c index cb70c625e2..d2e46729d1 100644 --- a/src/lib/usbdebug_direct.c +++ b/src/lib/usbdebug_direct.c @@ -87,7 +87,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug) /* Stop when the transaction is finished */ if (ctrl & DBGP_DONE) break; - } while(--loop>0); + } while(--loop>0); if (!loop) return -1000; @@ -132,7 +132,7 @@ retry: */ if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET)) dbgp_breath(); - + /* If I get a NACK reissue the transmission */ if (lpid == USB_PID_NAK) { if (--loop > 0) goto retry; @@ -179,7 +179,7 @@ static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, unsigned devnum, un pids = read32(&ehci_debug->pids); pids = DBGP_PID_UPDATE(pids, USB_PID_OUT); - + ctrl = read32(&ehci_debug->control); ctrl = DBGP_LEN_UPDATE(ctrl, size); ctrl |= DBGP_OUT; @@ -213,12 +213,12 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum, uns pids = read32(&ehci_debug->pids); pids = DBGP_PID_UPDATE(pids, USB_PID_IN); - + ctrl = read32(&ehci_debug->control); ctrl = DBGP_LEN_UPDATE(ctrl, size); ctrl &= ~DBGP_OUT; ctrl |= DBGP_GO; - + write32(&ehci_debug->address, addr); write32(&ehci_debug->pids, pids); ret = dbgp_wait_until_done(ehci_debug, ctrl); @@ -234,7 +234,7 @@ int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size) return dbgp_bulk_read(dbg_info->ehci_debug, dbg_info->devnum, dbg_info->endpoint_in, data, size); } -static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype, int request, +static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype, int request, int value, int index, void *data, int size) { unsigned pids, addr, ctrl; @@ -245,7 +245,7 @@ static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, i read = (requesttype & USB_DIR_IN) != 0; if (size > (read?DBGP_MAX_PACKET:0)) return -1; - + /* Compute the control message */ req.bRequestType = requesttype; req.bRequest = request; @@ -298,7 +298,7 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port) loop = 2; write32(&ehci_regs->port_status[port - 1], portsc & ~(PORT_RWC_BITS | PORT_RESET)); - do { + do { dbgp_mdelay(delay); portsc = read32(&ehci_regs->port_status[port - 1]); delay_time += delay; @@ -395,7 +395,7 @@ try_next_port: set_debug_port(debug_port); goto try_next_time; } - return; + return; } /* Reset the EHCI controller */ @@ -492,7 +492,7 @@ try_next_port: USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, (void *)0, 0); if (ret < 0) { - dbgp_printk("Could not move attached device to %d.\n", + dbgp_printk("Could not move attached device to %d.\n", USB_DEBUG_DEVNUM); goto err; } @@ -525,7 +525,7 @@ try_next_port: info->devnum = devnum; info->endpoint_out = dbgp_endpoint_out; info->endpoint_in = dbgp_endpoint_in; - + return; err: /* Things didn't work so remove my claim */ diff --git a/src/lib/xmodem.c b/src/lib/xmodem.c index 465d6670a3..2d553bed03 100644 --- a/src/lib/xmodem.c +++ b/src/lib/xmodem.c @@ -143,7 +143,7 @@ int xmodemReceive(unsigned char *dest, int destsz) *p++ = c; } - if (xbuff[1] == (unsigned char)(~xbuff[2]) && + if (xbuff[1] == (unsigned char)(~xbuff[2]) && (xbuff[1] == packetno || xbuff[1] == (unsigned char)packetno-1) && check(crc, &xbuff[3], bufsz)) { if (xbuff[1] == packetno) { diff --git a/src/mainboard/a-trend/Kconfig b/src/mainboard/a-trend/Kconfig index f5a379f84d..7cb53924dd 100644 --- a/src/mainboard/a-trend/Kconfig +++ b/src/mainboard/a-trend/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_A_TREND - + source "src/mainboard/a-trend/atc-6220/Kconfig" source "src/mainboard/a-trend/atc-6240/Kconfig" diff --git a/src/mainboard/abit/Kconfig b/src/mainboard/abit/Kconfig index 982cc9eee7..1f704b84c3 100644 --- a/src/mainboard/abit/Kconfig +++ b/src/mainboard/abit/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_ABIT - + source "src/mainboard/abit/be6-ii_v2_0/Kconfig" endchoice diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb index 0c0c8f0c31..bc84dc0373 100644 --- a/src/mainboard/amd/rumba/devicetree.cb +++ b/src/mainboard/amd/rumba/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/gx2 device apic 0 on end end end - device pci_domain 0 on + device pci_domain 0 on device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 diff --git a/src/mainboard/amd/rumba/irq_tables.c b/src/mainboard/amd/rumba/irq_tables.c index 598350b4b8..f751b481ca 100644 --- a/src/mainboard/amd/rumba/irq_tables.c +++ b/src/mainboard/amd/rumba/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c index adb1786678..0e7bbb66e7 100644 --- a/src/mainboard/amd/rumba/mainboard.c +++ b/src/mainboard/amd/rumba/mainboard.c @@ -19,7 +19,7 @@ static void init(struct device *dev) { printk(BIOS_DEBUG, "AMD RUMBA ENTER %s\n", __func__); if (nicirq) { - printk(BIOS_DEBUG, "%s (%x,%x)SET PCI interrupt line to %d\n", + printk(BIOS_DEBUG, "%s (%x,%x)SET PCI interrupt line to %d\n", __func__, bus, devfn, nicirq); nic = dev_find_slot(bus, devfn); if (! nic){ diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index 813b009471..958cf3196c 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -35,7 +35,7 @@ static inline unsigned int fls(unsigned int x) return r; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * * component Banks (byte 17) * module banks, side (byte 5) * @@ -86,7 +86,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) msr = rdmsr(0x20000019); msr.hi = 0x18000108; msr.lo = 0x696332a3; - wrmsr(0x20000019, msr); + wrmsr(0x20000019, msr); } @@ -122,7 +122,7 @@ static void main(unsigned long bist) }; SystemPreInit(); - + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -134,7 +134,7 @@ static void main(unsigned long bist) cpuRegInit(); print_err("done cpuRegInit\n"); - + sdram_initialize(1, memctrl); msr_init(); diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl index b2474e2a20..77958b2063 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl @@ -4,17 +4,17 @@ //AMD8111 Name (APIC, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00} }) @@ -34,16 +34,16 @@ Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) - + Store (0x00, ^DNCG) - + } - If (LNot (PICF)) { - Return (PICM) + If (LNot (PICF)) { + Return (PICM) } Else { - Return (APIC) + Return (APIC) } } @@ -57,7 +57,7 @@ OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) Field (PIRQ, ByteAcc, Lock, Preserve) { - PIBA, 8, + PIBA, 8, PIDC, 8 } /* @@ -144,7 +144,7 @@ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } }) - + Name (PICM, Package (0x0C) { Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl index 9d93e34e92..9e952c80bd 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl @@ -5,7 +5,7 @@ Device (ISA) { - /* lpc 0x00040000 */ + /* lpc 0x00040000 */ Method (_ADR, 0, NotSerialized) { Return (DADD(\_SB.PCI0.SBDN, 0x00010000)) @@ -15,11 +15,11 @@ Field (PIRY, ByteAcc, NoLock, Preserve) { Z000, 2, // Parallel Port Range - , 1, + , 1, ECP, 1, // ECP Enable FDC1, 1, // Floppy Drive Controller 1 FDC2, 1, // Floppy Drive Controller 2 - Offset (0x01), + Offset (0x01), Z001, 3, // Serial Port A Range SAEN, 1, // Serial Post A Enabled Z002, 3, // Serial Port B Range @@ -106,7 +106,7 @@ IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) - IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error }) Method (_CRS, 0, NotSerialized) @@ -134,7 +134,7 @@ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS }) - // Read the Video Memory length + // Read the Video Memory length CreateDWordField (BUF0, 0x14, CLEN) CreateDWordField (BUF0, 0x10, CBAS) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl index e209665e48..172f0bf9d1 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,60 +19,60 @@ Name (APIC, Package (0x14) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, - + //Cypress Slot A - PIRQ BCDA Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //? - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 }, //Cypress Slot B - PIRQ CDAB Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //? - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 }, + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 }, //Cypress Slot C - PIRQ DABC Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //? - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 }, - Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A }, //Cypress Slot D - PIRQ ABCD Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //? - Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A }, Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B } }) Name (PICM, Package (0x14) { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) @@ -100,15 +100,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 }, Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl index 163c0f6061..8b8bc9fab9 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,18 +19,18 @@ Name (APIC, Package (0x04) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - + }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, }) Name (DNCG, Ones) @@ -40,7 +40,7 @@ If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 Store (0x00, Local1) - While (LLess (Local1, 0x04)) + While (LLess (Local1, 0x04)) { // Update the GSI according to HCIN Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) @@ -76,15 +76,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl index 75ef72343a..e5cfe3c951 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl @@ -1,7 +1,7 @@ /* * Copyright 2005 AMD */ - + Device (PG0A) { /* 8132 pcix bridge*/ @@ -19,18 +19,18 @@ Name (APIC, Package (0x04) { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - + }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, }) Name (DNCG, Ones) @@ -40,7 +40,7 @@ If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 Store (0x00, Local1) - While (LLess (Local1, 0x04)) + While (LLess (Local1, 0x04)) { // Update the GSI according to HCIN Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) @@ -76,15 +76,15 @@ { // Slot A - PIRQ ABCD Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl index 001d45b0fe..ce85502296 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl @@ -1,4 +1,4 @@ -// AMD8151 +// AMD8151 Device (AGPB) { Method (_ADR, 0, NotSerialized) @@ -8,16 +8,16 @@ Name (APIC, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } }) Name (PICM, Package (0x04) { - Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 } }) Method (_PRT, 0, NotSerialized) diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index c2b8e8c7b3..f132ec727c 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -4,7 +4,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb index b9742b4a46..c1748697f4 100644 --- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8132 # the on/off keyword is mandatory @@ -56,7 +56,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -120,7 +120,7 @@ chip northbridge/amd/amdk8/root_complex end # device pci 18.0 device pci 18.0 on end - device pci 18.0 on end + device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/amd/serengeti_cheetah/dsdt.asl b/src/mainboard/amd/serengeti_cheetah/dsdt.asl index ee87023ff8..a549d70297 100644 --- a/src/mainboard/amd/serengeti_cheetah/dsdt.asl +++ b/src/mainboard/amd/serengeti_cheetah/dsdt.asl @@ -100,11 +100,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) + Return (Local3) } #include "acpi/pci0_hc.asl" - + } Device (PCI1) { @@ -138,7 +138,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) Notify (\_SB.PCI0.PG0B, 0x02) } - Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A + Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A { Notify (\_SB.PCI0.PG0A, 0x02) } @@ -183,14 +183,14 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) Field (GRAM, ByteAcc, Lock, Preserve) { - Offset (0x10), + Offset (0x10), FLG0, 8 } OperationRegion (GSTS, SystemIO, 0xC028, 0x02) Field (GSTS, ByteAcc, NoLock, Preserve) { - , 4, + , 4, IRQR, 1 } diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c index d4c6622847..6b6107070b 100644 --- a/src/mainboard/amd/serengeti_cheetah/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah/fadt.c @@ -30,7 +30,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ // 3=Workstation,4=Enterprise Server, 7=Performance Server fadt->preferred_pm_profile=0x03; fadt->sci_int=9; - // disable system management mode by setting to 0: + // disable system management mode by setting to 0: fadt->smi_cmd = 0;//pm_base+0x2f; fadt->acpi_enable = 0xf0; fadt->acpi_disable = 0xf1; @@ -53,7 +53,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe0_blk_len = 4; fadt->gpe1_blk_len = 8; fadt->gpe1_base = 16; - + fadt->cst_cnt = 0xe3; fadt->p_lvl2_lat = 101; fadt->p_lvl3_lat = 1001; @@ -66,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->century = 0; // 0x7f to make rtc alrm work fadt->iapc_boot_arch = 0x3; // See table 5-11 fadt->flags = 0x25; - + fadt->res2 = 0; fadt->reset_reg.space_id = 1; diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index 436044e69a..3674ff0076 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -15,7 +15,7 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables struct mb_sysconf_t mb_sysconf; -static unsigned pci1234x[] = +static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -27,7 +27,7 @@ static unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -static unsigned hcdnx[] = +static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -88,17 +88,17 @@ void get_bus_conf(void) get_bus_conf_done = 1; sysconf.mb = &mb_sysconf; - + m = sysconf.mb; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i> 8) & 0xff; m->sbdn3 = sysconf.hcdn[0] & 0xff; @@ -209,8 +209,8 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif m->apicid_8111 = apicid_base+0; m->apicid_8132_1 = apicid_base+1; diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c index d872b0a0db..637f980055 100644 --- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -13,11 +13,11 @@ #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; @@ -50,7 +50,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct mb_sysconf_t *m; get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c - + m = sysconf.mb; /* Align the table to be 16 byte aligned. */ @@ -62,25 +62,25 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_8111_0; pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1022; pirq->rtr_device = 0x746b; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); - + pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; - + { device_t dev; dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3)); @@ -126,11 +126,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) j++; } - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 2b2f65c39b..fe2f9440e2 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -101,8 +101,8 @@ static void *smp_write_config_table(void *v) } } - -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + +/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_8111, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x2); diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt index 41988c8ede..685cd7a2ce 100644 --- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt +++ b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt @@ -6,7 +6,7 @@ At this time, For acpi support We got The developers need to change for different MB -Change dsdt.asl, according to MB layout +Change dsdt.asl, according to MB layout pci1, pci2, pci3, pci4, ...., pci8 if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c @@ -17,7 +17,7 @@ Change acpi_tables.c Regarding pci bridge apic and pic need to modify entries amd8111.asl and amd8131.asl and amd8151.asl.... acording to your MB laybout, it is like that in mptable.c -About other chipsets, need to develop their special asl such as +About other chipsets, need to develop their special asl such as ck804.asl --- NB ck804 bcm5785.asl or bcm5780.asl ---- Serverworks HT1000/HT2000 @@ -27,4 +27,4 @@ use c to delele hex file yhlu 09/18/2005 - + diff --git a/src/mainboard/amd/serengeti_cheetah/resourcemap.c b/src/mainboard/amd/serengeti_cheetah/resourcemap.c index 9b19503360..be11b689da 100644 --- a/src/mainboard/amd/serengeti_cheetah/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah/resourcemap.c @@ -143,7 +143,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -199,7 +199,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -207,7 +207,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 00d4b3b21a..6fcaa90875 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -1,7 +1,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 @@ -107,7 +107,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -186,7 +186,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -201,21 +201,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) + * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn @@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt2.asl b/src/mainboard/amd/serengeti_cheetah/ssdt2.asl index 582ef97621..791454c190 100644 --- a/src/mainboard/amd/serengeti_cheetah/ssdt2.asl +++ b/src/mainboard/amd/serengeti_cheetah/ssdt2.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt3.asl b/src/mainboard/amd/serengeti_cheetah/ssdt3.asl index 583e945740..28fe5f45a3 100644 --- a/src/mainboard/amd/serengeti_cheetah/ssdt3.asl +++ b/src/mainboard/amd/serengeti_cheetah/ssdt3.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt4.asl b/src/mainboard/amd/serengeti_cheetah/ssdt4.asl index fd7224d17a..93abb7f520 100644 --- a/src/mainboard/amd/serengeti_cheetah/ssdt4.asl +++ b/src/mainboard/amd/serengeti_cheetah/ssdt4.asl @@ -28,16 +28,16 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) // BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 - + Name (_UID, 0xdd) // HC 0x03 - Name (_HID, "PNP0A03") + Name (_HID, "PNP0A03") Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) } - + Method (_BBN, 0, NotSerialized) { Return (GBUS (GHCN(HCIN), GHCL(HCIN))) @@ -45,7 +45,7 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) Method (_STA, 0, NotSerialized) { - Return (\_SB.GHCE(HCIN)) + Return (\_SB.GHCE(HCIN)) } Method (_CRS, 0, NotSerialized) diff --git a/src/mainboard/arima/Kconfig b/src/mainboard/arima/Kconfig index d1979b00a2..8895433a55 100644 --- a/src/mainboard/arima/Kconfig +++ b/src/mainboard/arima/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_ARIMA - + source "src/mainboard/arima/hdama/Kconfig" endchoice diff --git a/src/mainboard/arima/hdama/debug.c b/src/mainboard/arima/hdama/debug.c index 0db327c5c6..a6f0d558a8 100644 --- a/src/mainboard/arima/hdama/debug.c +++ b/src/mainboard/arima/hdama/debug.c @@ -12,8 +12,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -32,7 +32,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -51,8 +51,8 @@ static void dump_pci_device(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -77,10 +77,10 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr device = ctrl[n].channel0[i]; if (device) { int j; - print_debug("dimm: "); + print_debug("dimm: "); print_debug_hex8(n); print_debug_char('.'); - print_debug_hex8(i); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -109,10 +109,10 @@ static void dump_spd_registers(int controllers, const struct mem_controller *ctr device = ctrl[n].channel1[i]; if (device) { int j; - print_debug("dimm: "); + print_debug("dimm: "); print_debug_hex8(n); print_debug_char('.'); - print_debug_hex8(i); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { diff --git a/src/mainboard/arima/hdama/devicetree.cb b/src/mainboard/arima/hdama/devicetree.cb index a812814782..0ab47a4f0b 100644 --- a/src/mainboard/arima/hdama/devicetree.cb +++ b/src/mainboard/arima/hdama/devicetree.cb @@ -6,14 +6,14 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on # PCIX bridge ## On board NIC A #chip drivers/generic/generic - # device pci 3.0 on + # device pci 3.0 on # irq 0 = 0x13 # end #end @@ -31,7 +31,7 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x13 # irq 3 = 0x10 # end - #end + #end ## PCI Slot 4 #chip drivers/generic/generic # device pci 2.0 on @@ -40,7 +40,7 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x10 # irq 3 = 0x11 # end - #end + #end end device pci 0.1 on end # IOAPIC device pci 1.0 on # PCIX bridge @@ -61,7 +61,7 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x10 # irq 3 = 0x11 # end - #end + #end end device pci 1.1 on end # IOAPIC end @@ -82,7 +82,7 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x13 # irq 3 = 0x10 # end - #end + #end ## PCI Slot 6 (correct?) #chip drivers/generic/generic # device pci 4.0 on @@ -91,13 +91,13 @@ chip northbridge/amd/amdk8/root_complex # irq 2 = 0x12 # irq 3 = 0x13 # end - #end + #end end # LPC bridge device pci 1.0 on chip superio/nsc/pc87360 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -124,7 +124,7 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.7 off end # GPIO device pnp 2e.8 off end # ACB device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT + device pnp 2e.a off end # WDT end end device pci 1.1 on end # IDE @@ -132,8 +132,8 @@ chip northbridge/amd/amdk8/root_complex device pci 1.3 on # System Management chip drivers/generic/generic #phillips pca9545 smbus mux - device i2c 70 on - # analog_devices adm1026 + device i2c 70 on + # analog_devices adm1026 chip drivers/generic/generic device i2c 2c on end end @@ -147,33 +147,33 @@ chip northbridge/amd/amdk8/root_complex end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end + device i2c 54 on end end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end - end + end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end device pci 1.5 off end # AC97 Audio device pci 1.6 on end # AC97 Modem register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.0 on end # LDT1 device pci 18.0 on end # LDT2 device pci 18.1 on end @@ -188,6 +188,6 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end - end + end end diff --git a/src/mainboard/arima/hdama/irq_tables.c b/src/mainboard/arima/hdama/irq_tables.c index 2ca98066d0..ba516f88e2 100644 --- a/src/mainboard/arima/hdama/irq_tables.c +++ b/src/mainboard/arima/hdama/irq_tables.c @@ -12,7 +12,7 @@ {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0} /* Each IRQ_SLOT entry consists of: - * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu + * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ const struct irq_routing_table intel_irq_routing_table = { diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 643dfabd5d..11b8063f95 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #define HT_INIT_CONTROL 0x6c @@ -26,7 +26,7 @@ static void smp_write_processors_inorder(struct mp_config_table *mc) unsigned cpu_feature_flags; struct cpuid_result result; device_t cpu; - + boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; result = cpuid(1); @@ -57,7 +57,7 @@ static void smp_write_processors_inorder(struct mp_config_table *mc) } } } - + static unsigned node_link_to_bus(unsigned node, unsigned link) { device_t dev; @@ -79,12 +79,12 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); #endif - if ((dst_node == node) && (dst_link == link)) + if ((dst_node == node) && (dst_link == link)) { return bus_base; } diff --git a/src/mainboard/artecgroup/Kconfig b/src/mainboard/artecgroup/Kconfig index 5f1a6e906f..e95e56a055 100644 --- a/src/mainboard/artecgroup/Kconfig +++ b/src/mainboard/artecgroup/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_ARTEC_GROUP - + source "src/mainboard/artecgroup/dbe61/Kconfig" endchoice diff --git a/src/mainboard/artecgroup/dbe61/spd_table.h b/src/mainboard/artecgroup/dbe61/spd_table.h index 33c9237836..73c777c9c4 100644 --- a/src/mainboard/artecgroup/dbe61/spd_table.h +++ b/src/mainboard/artecgroup/dbe61/spd_table.h @@ -27,7 +27,7 @@ struct spd_entry { /* Save space by using a short list of SPD values used by Geode LX Memory init */ /* 128MB */ -const struct spd_entry spd_table [] = +const struct spd_entry spd_table [] = { {SPD_MEMORY_TYPE, 0x07}, /* (Fundamental) memory type */ {SPD_NUM_ROWS, 0x0D}, /* Number of row address bits */ diff --git a/src/mainboard/asus/a8n_e/irq_tables.c b/src/mainboard/asus/a8n_e/irq_tables.c index 0c0d3467a2..ce15efd1a8 100644 --- a/src/mainboard/asus/a8n_e/irq_tables.c +++ b/src/mainboard/asus/a8n_e/irq_tables.c @@ -67,7 +67,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) uint8_t *v, sum = 0; int i; - /* get_bus_conf() will find out all bus num and APIC that share with + /* get_bus_conf() will find out all bus num and APIC that share with * mptable.c and mptable.c. */ get_bus_conf(); diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c index de957a8f78..e7e6bb40f7 100644 --- a/src/mainboard/asus/a8v-e_se/acpi_tables.c +++ b/src/mainboard/asus/a8v-e_se/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Written by Stefan Reinauer . - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * * Copyright (C) 2004 Stefan Reinauer * Copyright (C) 2005 Nick Barker @@ -71,7 +71,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* IRQ0 -> APIC IRQ2. */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); + current, 0, 0, 2, 0x0); /* Create all subtables for processors. */ current = acpi_create_madt_lapic_nmis(current, diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 3ec90f8010..f571bae472 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -5,7 +5,7 @@ * (Written by Yinghai Lu for AMD) * Copyright (C) 2006 MSI * (Written by Bingxun Shi for MSI) - * Copyright (C) 2007 Rudolf Marek + * Copyright (C) 2007 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) }; unsigned bsp_apicid = 0; int needs_reset = 0; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c index 46a6c1f6a4..1862bc993f 100644 --- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c +++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Written by Stefan Reinauer . - * ACPI FADT, FACS, and DSDT table support added by + * ACPI FADT, FACS, and DSDT table support added by * * Copyright (C) 2004 Stefan Reinauer * Copyright (C) 2005 Nick Barker @@ -73,7 +73,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* IRQ0 -> APIC IRQ2. */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0x0); + current, 0, 0, 2, 0x0); /* Create all subtables for processors. */ current = acpi_create_madt_lapic_nmis(current, diff --git a/src/mainboard/asus/m2v-mx_se/dsdt.asl b/src/mainboard/asus/m2v-mx_se/dsdt.asl index fd4d42d378..493f1d6c8f 100644 --- a/src/mainboard/asus/m2v-mx_se/dsdt.asl +++ b/src/mainboard/asus/m2v-mx_se/dsdt.asl @@ -60,7 +60,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Name (_ADR, 0x00) Name (_UID, 0x00) Name (_BBN, 0x00) - + External (BUSN) External (MMIO) External (PCIO) @@ -95,7 +95,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) - Return (Local3) + Return (Local3) } /* PCI Routing Table */ @@ -185,7 +185,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) /* two LSB bits are blink rate */ LEDR, 2, } - + /* PS/2 keyboard (seems to be important for WinXP install) */ Device (KBD) { diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 04a5206437..ea9870798c 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -5,7 +5,7 @@ * (Written by Yinghai Lu for AMD) * Copyright (C) 2006 MSI * (Written by Bingxun Shi for MSI) - * Copyright (C) 2008 Rudolf Marek + * Copyright (C) 2008 Rudolf Marek * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb index a5415a2bfe..29d706c62a 100644 --- a/src/mainboard/asus/mew-vm/devicetree.cb +++ b/src/mainboard/asus/mew-vm/devicetree.cb @@ -1,5 +1,5 @@ chip northbridge/intel/i82810 - device pci_domain 0 on + device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on # Onboard Video # device pci 1.0 on end diff --git a/src/mainboard/asus/mew-vm/irq_tables.c b/src/mainboard/asus/mew-vm/irq_tables.c index 3bd0d7195f..259b0e4938 100644 --- a/src/mainboard/asus/mew-vm/irq_tables.c +++ b/src/mainboard/asus/mew-vm/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up * @@ -18,7 +18,7 @@ const struct irq_routing_table intel_irq_routing_table = { 0x7120, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x89, /* u8 checksum , this has to set to some value + 0x89, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ diff --git a/src/mainboard/azza/Kconfig b/src/mainboard/azza/Kconfig index f7109ecbf7..0c0be97d46 100644 --- a/src/mainboard/azza/Kconfig +++ b/src/mainboard/azza/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_AZZA - + source "src/mainboard/azza/pt-6ibd/Kconfig" endchoice diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 73bdfc20d8..85fad0a4f1 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_BIOSTAR - + source "src/mainboard/biostar/m6tba/Kconfig" endchoice diff --git a/src/mainboard/broadcom/Kconfig b/src/mainboard/broadcom/Kconfig index bf956ecdb3..d7406c0b45 100644 --- a/src/mainboard/broadcom/Kconfig +++ b/src/mainboard/broadcom/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_BROADCOM - + source "src/mainboard/broadcom/blast/Kconfig" endchoice diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb index a9cabe6bea..d06c590bf8 100644 --- a/src/mainboard/broadcom/blast/devicetree.cb +++ b/src/mainboard/broadcom/blast/devicetree.cb @@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex end device pci_domain 0 on chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 0 chip southbridge/broadcom/bcm5780 # HT2000 device pci 0.0 on end # PXB 1 0x0130 @@ -95,7 +95,7 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.10 on #RTC io 0x60 = 0x70 io 0x62 = 0x72 - end + end end end device pci 1.3 on end # WDTimer 0x0238 @@ -110,7 +110,7 @@ chip northbridge/amd/amdk8/root_complex end # device pci 18.0 device pci 18.0 on end - device pci 18.0 on end + device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c index 9d1a4b1bf0..06f42f4092 100644 --- a/src/mainboard/broadcom/blast/get_bus_conf.c +++ b/src/mainboard/broadcom/blast/get_bus_conf.c @@ -21,7 +21,7 @@ unsigned char bus_bcm5785_1_1 = 9; unsigned apicid_bcm5785[3]; -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -115,9 +115,9 @@ void get_bus_conf(void) /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - for(i=0;i<3;i++) + for(i=0;i<3;i++) apicid_bcm5785[i] = apicid_base+i; } diff --git a/src/mainboard/broadcom/blast/irq_tables.c b/src/mainboard/broadcom/blast/irq_tables.c index 3f6f73893e..406419d6d8 100644 --- a/src/mainboard/broadcom/blast/irq_tables.c +++ b/src/mainboard/broadcom/blast/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -16,7 +16,7 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; @@ -64,22 +64,22 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_bcm5785_0; pirq->rtr_devfn = (sysconf.sbdn<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x1166; pirq->rtr_device = 0x0036; pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); - + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c pirq_info = (void *) ( &pirq->checksum + 1); @@ -87,11 +87,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_bcm5785_0, (sysconf.sbdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index 8a1b133bfb..d24630844e 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -72,12 +72,12 @@ static void *smp_write_config_table(void *v) } } } - + } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_bcm5785[0], 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_bcm5785[0], 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_bcm5785[0], 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_bcm5785[0], 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_bcm5785[0], 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_bcm5785[0], 0x4); @@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_bcm5785[0], 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_bcm5785[0], 0xd); -//IDE +//IDE outb(0x02, 0xc00); outb(0x0e, 0xc01); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE @@ -97,14 +97,14 @@ static void *smp_write_config_table(void *v) //SATA outb(0x07, 0xc00); outb(0x0f, 0xc01); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf); - + //USB outb(0x01, 0xc00); outb(0x0a, 0xc01); for(i=0;i<3;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); // } - + /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ @@ -127,13 +127,13 @@ static void *smp_write_config_table(void *v) } -//pci slot (on bcm5785) +//pci slot (on bcm5785) for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); // } -//onboard ati +//onboard ati smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1); //PCI-X on bcm5780 @@ -157,7 +157,7 @@ static void *smp_write_config_table(void *v) } -// Second PCI-E x8 +// Second PCI-E x8 for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); // } diff --git a/src/mainboard/broadcom/blast/resourcemap.c b/src/mainboard/broadcom/blast/resourcemap.c index 438605c701..71f0bba010 100644 --- a/src/mainboard/broadcom/blast/resourcemap.c +++ b/src/mainboard/broadcom/blast/resourcemap.c @@ -119,7 +119,7 @@ static void setup_blast_resource_map(void) PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -144,7 +144,7 @@ static void setup_blast_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -181,7 +181,7 @@ static void setup_blast_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -200,7 +200,7 @@ static void setup_blast_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_blast_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -252,8 +252,8 @@ static void setup_blast_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 35823bd47c..13f5f97414 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -3,7 +3,7 @@ #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif - + #include #include #include @@ -75,7 +75,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -109,7 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct mem_controller ctrl[8]; unsigned nodes; - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -130,7 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); // post_code(0x33); - + uart_init(); // post_code(0x34); @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); setup_blast_resource_map(); - + #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); @@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); -#if 0 +#if 0 int i; for(i=4;i<8;i++) { change_i2c_mux(i); diff --git a/src/mainboard/compaq/Kconfig b/src/mainboard/compaq/Kconfig index 160048f30f..c2bbb57120 100644 --- a/src/mainboard/compaq/Kconfig +++ b/src/mainboard/compaq/Kconfig @@ -21,7 +21,7 @@ choice prompt "Mainboard model" depends on VENDOR_COMPAQ - + source "src/mainboard/compaq/deskpro_en_sff_p600/Kconfig" endchoice diff --git a/src/mainboard/dell/s1850/debug.c b/src/mainboard/dell/s1850/debug.c index 2ea3db32ea..45315618b7 100644 --- a/src/mainboard/dell/s1850/debug.c +++ b/src/mainboard/dell/s1850/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,7 +215,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -228,7 +228,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -248,7 +248,7 @@ void show_dram_slots(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + status = smbus_read_byte(device, 0); if (status < 0) { print_debug("bad device: "); @@ -272,7 +272,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -280,7 +280,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -288,4 +288,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/dell/s1850/devicetree.cb b/src/mainboard/dell/s1850/devicetree.cb index ab95e54a7b..bd7b3a3773 100644 --- a/src/mainboard/dell/s1850/devicetree.cb +++ b/src/mainboard/dell/s1850/devicetree.cb @@ -1,23 +1,23 @@ chip northbridge/intel/e7520 # mch - device pci_domain 0 on + device pci_domain 0 on chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end - device pci 1d.2 on end + device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end - + # -> Bridge device pci 1e.0 on end - + # -> ISA - device pci 1f.0 on + device pci 1f.0 on chip superio/nsc/pc8374 device pnp 2e.0 off end device pnp 2e.1 off end device pnp 2e.2 off end - device pnp 2e.3 on + device pnp 2e.3 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -30,22 +30,22 @@ chip northbridge/intel/e7520 # mch end # -> IDE device pci 1f.1 on end - # -> SATA + # -> SATA device pci 1f.2 on end device pci 1f.3 on end register "pirq_a_d" = "0x8a07030b" register "pirq_e_h" = "0x85808080" end - device pci 00.0 on end + device pci 00.0 on end device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on + device pci 01.0 on end + device pci 02.0 on chip southbridge/intel/pxhd # pxhd1 # Bus bridges and ioapics usually bus 1 - device pci 0.0 on + device pci 0.0 on # On board gig e1000 - chip drivers/generic/generic + chip drivers/generic/generic device pci 03.0 on end device pci 03.1 on end end diff --git a/src/mainboard/dell/s1850/irq_tables.c b/src/mainboard/dell/s1850/irq_tables.c index 8b4773df66..1f56ed30b9 100644 --- a/src/mainboard/dell/s1850/irq_tables.c +++ b/src/mainboard/dell/s1850/irq_tables.c @@ -1,8 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) by the coreboot pirq tool. - * This file was programatically generated. + * Copyright (C) by the coreboot pirq tool. + * This file was programatically generated. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c index c7fd52af3e..4cdd0f1e7b 100644 --- a/src/mainboard/dell/s1850/mptable.c +++ b/src/mainboard/dell/s1850/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -98,9 +98,9 @@ static void *smp_write_config_table(void *v) bus_pxhd_4 = 6; } - + } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -135,7 +135,7 @@ static void *smp_write_config_table(void *v) else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); } - } + } /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, 0x02, 0x00); diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c index 199c6ea5d5..07fbef282d 100644 --- a/src/mainboard/dell/s1850/romstage.c +++ b/src/mainboard/dell/s1850/romstage.c @@ -65,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static inline void ibfzero(void) { - while(inb(ipmicsr) & (1<