From 15ca9034b39a7fe0d883c0406d3c7591163d33f4 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 5 Nov 2020 10:09:07 -0800 Subject: soc/intel/common/block/cse: Clear post code before reset To avoid "unknown post code 0x55" entries in the event log on cold boot clear the post code before doing the CSE initiated reset. Signed-off-by: Duncan Laurie Change-Id: I68078c04230dbc24f9cc63b1ef5c435055aa1186 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47257 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/cse/cse.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ef6db3da4f..d10492bbe0 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -555,6 +555,9 @@ int heci_reset(void) { uint32_t csr; + /* Clear post code to prevent eventlog entry from unknown code. */ + post_code(0); + /* Send reset request */ csr = read_host_csr(); csr |= (CSR_RESET | CSR_IG); -- cgit v1.2.3