From 19f5201463ff3ffe26754a69df493a37a6c96a05 Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Tue, 29 Jan 2019 01:54:38 +0530 Subject: mainboard/intel/cannonlake_rvp: Enable SaGv config This patch enables SaGv on Intel CNL-Y and CNL-U RVP board Change-Id: I8a4b8a2a365caed304935bf0d66db9a92d10c23f Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/31132 Reviewed-by: Furquan Shaikh Reviewed-by: Pratikkumar V Prajapati Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 2 +- src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 9604210794..e5f867cbdc 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -5,7 +5,7 @@ chip soc/intel/cannonlake end # FSP configuration - register "SaGv" = "SaGv_FixedHigh" + register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index e2ebaba1cb..a6d329be82 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -5,7 +5,7 @@ chip soc/intel/cannonlake end # FSP configuration - register "SaGv" = "SaGv_FixedHigh" + register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" -- cgit v1.2.3