From 1ad159094bb3445e0def0f94b38cbcc57d6e9db0 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 26 Feb 2020 00:40:42 +0530 Subject: mb/google/dedede: configure ESPI IO decode range for chrome EC Configure below ESPI IO decode ranges: 1. 0x200-020F: EC host command range. 2. 0x800-0x8FF: EC host command args and params. 3. 0x900-0x9ff: EC memory map range. Change-Id: I1e450d6e45242180de715746b9852634de2669c6 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39121 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: V Sowmya Reviewed-by: Subrata Banik Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2529e53feb..d5f58bae3e 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -20,6 +20,12 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_C" register "pmc_gpe0_dw2" = "GPP_D" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + # USB Port Configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 -- cgit v1.2.3