From 21aece86533093ec01a64be42fcb0fe23d5281b8 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 26 May 2020 17:02:37 -0700 Subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro This adds Type-C IO Manageability engine base address and size. Tigerlake EDS(#575681) section 3.4.3 describes host bridge REGBAR(MCHBAR) + 7110h for IOM REGBAR with size 1600h. IOM has a port ID 0xc1. MCHBAR is programmed with 0xfedc0000. IOM REGBAR is determined from mmio (MCHBAR + 0x7110), which has value 0xfb000000. IOM has base address 0xfbc10000 from IOM REGBAR + (0xc1 << 16). BUG=:b:156016218 TEST=Built and booted on Volteer. Signed-off-by: John Zhao Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41759 Reviewed-by: Tim Wawrzynczak Reviewed-by: Wonkyu Kim Reviewed-by: Rajmohan Mani Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/include/soc/iomap.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 282092fade..cd964f0d76 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -84,6 +84,8 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) +#define IOM_BASE_ADDRESS 0xfbc10000 +#define IOM_BASE_SIZE 0x1600 /* * I/O port address space -- cgit v1.2.3