From 274dabd7a04b18bc2f2378bb9faa7416dfd0ab83 Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Tue, 14 May 2019 12:55:17 +0200
Subject: src/northbridge: Remove unneeded include <arch/io.h>
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Change-Id: I52ace93ae6f802723823955ac349ed54dc064aaa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/northbridge/intel/gm45/early_reset.c        | 1 -
 src/northbridge/intel/gm45/romstage.c           | 1 -
 src/northbridge/intel/haswell/raminit.c         | 1 -
 src/northbridge/intel/i945/raminit.c            | 1 -
 src/northbridge/intel/pineview/raminit.c        | 1 -
 src/northbridge/intel/pineview/romstage.c       | 1 -
 src/northbridge/intel/sandybridge/raminit.c     | 1 -
 src/northbridge/intel/sandybridge/raminit_mrc.c | 1 -
 src/northbridge/intel/sandybridge/romstage.c    | 1 -
 src/northbridge/intel/x4x/raminit.c             | 1 -
 10 files changed, 10 deletions(-)

(limited to 'src')

diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index 3f095a256f..b5aa8044be 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -15,7 +15,6 @@
  */
 
 #include <types.h>
-#include <arch/io.h>
 #include <cf9_reset.h>
 #include <device/pci_ops.h>
 
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index 15d3c3a344..38f2d5f68f 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -18,7 +18,6 @@
 #include <cbmem.h>
 #include <romstage_handoff.h>
 #include <console/console.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <arch/acpi.h>
 #include <cpu/x86/lapic.h>
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 96dc94e7d2..050dbd1ae6 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -15,7 +15,6 @@
 
 #include <console/console.h>
 #include <string.h>
-#include <arch/io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
 #include <cbfs.h>
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 74407c14ff..797ea1229d 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -18,7 +18,6 @@
 #include <cpu/x86/cache.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include <cf9_reset.h>
 #include <device/mmio.h>
 #include <device/device.h>
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 144905fb92..282765efcc 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <cf9_reset.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index a3e6c39172..41fb0f6720 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -17,7 +17,6 @@
  * so this one is named with prefix mainboard.
  */
 
-#include <arch/io.h>
 #include <timestamp.h>
 #include <console/console.h>
 #include <device/pci_ops.h>
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index e60c37875b..2ebeaf0dca 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -21,7 +21,6 @@
 #include <cf9_reset.h>
 #include <string.h>
 #include <arch/cpu.h>
-#include <arch/io.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index a35d9d814e..f032b8aefc 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -18,7 +18,6 @@
 #include <bootmode.h>
 #include <cf9_reset.h>
 #include <string.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cbmem.h>
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 064d042e56..76b3088388 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -17,7 +17,6 @@
 
 #include <stdint.h>
 #include <console/console.h>
-#include <arch/io.h>
 #include <cf9_reset.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/lapic.h>
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 60d3b55531..7fed1efe26 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include <cf9_reset.h>
-- 
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