From 29f391ec8f37e3e7d838bf2d16a4ba190062f1dc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Mar 2020 22:51:05 +0100 Subject: nb/intel/sandybridge: Add print for PLL_REF100_CFG This field can take eight different values, depending on the maximum supported speed for the memory when using the 100 MHz reference clock. Change-Id: I8f2f04f9444831319d4f7bf0d246d01030b6f864 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39788 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/sandybridge/raminit_ivy.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 6ff82dd011..7d684b2d0e 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -176,10 +176,12 @@ static void find_cas_tck(ramctr_timing *ctrl) /* 100 MHz reference clock supported */ reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); - ref_100mhz_support = !!((reg32 >> 21) & 0x7); + ref_100mhz_support = (reg32 >> 21) & 0x7; printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes" : "no"); + printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); + /* Find CAS latency */ while (1) { /* -- cgit v1.2.3