From 2d92b1a3b1f2f42f36e035163b4658d440a082e1 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 6 Dec 2018 17:12:40 -0800 Subject: mb/google/sarien: Disable PCH Gigabit LAN There's no LAN connection on Arcada board, so disable PCH GBE. BUG=N/A Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/c/30096 Tested-by: build bot (Jenkins) Reviewed-by: Bora Guvendik --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index fccec9f3b6..924f51d17f 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -78,11 +78,6 @@ chip soc/intel/cannonlake }, }" - # PCIe port 9 for LAN - register "PcieRpEnable[8]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN" - register "PcieClkSrcClkReq[0]" = "0" - # PCIe port 10 for M.2 2230 WLAN register "PcieRpEnable[9]" = "1" register "PcieClkSrcUsage[2]" = "9" @@ -250,6 +245,6 @@ chip soc/intel/cannonlake device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device pci 1f.6 off end # GbE end end -- cgit v1.2.3