From 3054a1927983ef07cbc147ba776ea5d990571bdd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 28 Dec 2020 15:00:39 +0100 Subject: soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Correct the mask for the power cycle delay from 0xff to 0x1f, to represent the actual maximum value according to Intel graphics PRM for Haswell, Volume 2c and Intel graphics PRM for Broadwell, Volume 2c. Change-Id: Ib187f1ca6474325475e5ae4cc1b2ffbce12f10bf Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/48957 Reviewed-by: Matt DeVillier Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/gma.c | 4 ++-- src/soc/intel/broadwell/gma.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 0bca230b64..71d5ab61ec 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -273,8 +273,8 @@ static void gma_setup_panel(struct device *dev) /* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { reg32 = gtt_read(PCH_PP_DIVISOR); - reg32 &= ~0xff; - reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; + reg32 &= ~0x1f; + reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; gtt_write(PCH_PP_DIVISOR, reg32); } diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index d42eebc4f1..c033b499f5 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -314,8 +314,8 @@ static void gma_setup_panel(struct device *dev) /* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { reg32 = gtt_read(PCH_PP_DIVISOR); - reg32 &= ~0xff; - reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; + reg32 &= ~0x1f; + reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; gtt_write(PCH_PP_DIVISOR, reg32); } -- cgit v1.2.3