From 3449fafec3123e4bdf117c79e15dfd74bc695e27 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 22 Jan 2019 15:47:26 +0100 Subject: nb/intel/i945: Remove 2nd write on SLOTCAP (R/WO) SLOTCAP is R/WO, it becomes RO after the first write. Write already done on line #583. Tested using kprint before and after on 945G-M4 board. Change-Id: I27579bc634e357490defabb041457aaa010fb1c8 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/31036 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/i945/early_init.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src') diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 7ab252585a..e8cacf622f 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -552,8 +552,6 @@ static void i945_setup_pci_express_x16(void) u32 reg32; u16 reg16; - u8 reg8; - printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); @@ -733,9 +731,6 @@ static void i945_setup_pci_express_x16(void) reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); - reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), SLOTCAP); - pci_write_config8(PCI_DEV(0, 0x01, 0), SLOTCAP, reg8); - /* Additional PCIe graphics setup */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); reg32 |= (3 << 26); -- cgit v1.2.3