From 37a8a8bd9e9d37da1e899297dbb43c0033cfd6c4 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Tue, 21 May 2013 14:51:26 -0500 Subject: Add support for VIA EPIA-M850 board EPIA-M850 can now boot linux. For a list of issues, see: http://www.coreboot.org/VIA_EPIA-M850 That's all folks. Change-Id: I7624944dbc05fbf3019897a116954d71dfda0031 Signed-off-by: Alexandru Gagniuc Reviewed-on: http://review.coreboot.org/1228 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/mainboard/via/Kconfig | 6 ++ src/mainboard/via/epia-m850/Kconfig | 49 +++++++++++ src/mainboard/via/epia-m850/Makefile.inc | 21 +++++ src/mainboard/via/epia-m850/devicetree.cb | 111 +++++++++++++++++++++++++ src/mainboard/via/epia-m850/irq_tables.c | 75 +++++++++++++++++ src/mainboard/via/epia-m850/mainboard.c | 111 +++++++++++++++++++++++++ src/mainboard/via/epia-m850/romstage.c | 130 ++++++++++++++++++++++++++++++ 7 files changed, 503 insertions(+) create mode 100644 src/mainboard/via/epia-m850/Kconfig create mode 100644 src/mainboard/via/epia-m850/Makefile.inc create mode 100644 src/mainboard/via/epia-m850/devicetree.cb create mode 100644 src/mainboard/via/epia-m850/irq_tables.c create mode 100644 src/mainboard/via/epia-m850/mainboard.c create mode 100644 src/mainboard/via/epia-m850/romstage.c (limited to 'src') diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig index 69805482d9..d8f280b048 100644 --- a/src/mainboard/via/Kconfig +++ b/src/mainboard/via/Kconfig @@ -9,6 +9,11 @@ config BOARD_VIA_EPIA_CN bool "EPIA-CN" config BOARD_VIA_EPIA_M700 bool "EPIA-M700" +config BOARD_VIA_EPIA_M850 + bool "EPIA-M850" + help + STOP RIGHT HERE AND READ THIS!!! + Read http://www.coreboot.org/VIA_EPIA-M850 before you proceed. config BOARD_VIA_EPIA_M bool "EPIA-M" config BOARD_VIA_EPIA_N @@ -23,6 +28,7 @@ endchoice source "src/mainboard/via/epia/Kconfig" source "src/mainboard/via/epia-cn/Kconfig" source "src/mainboard/via/epia-m700/Kconfig" +source "src/mainboard/via/epia-m850/Kconfig" source "src/mainboard/via/epia-m/Kconfig" source "src/mainboard/via/epia-n/Kconfig" source "src/mainboard/via/pc2500e/Kconfig" diff --git a/src/mainboard/via/epia-m850/Kconfig b/src/mainboard/via/epia-m850/Kconfig new file mode 100644 index 0000000000..01ef032c4e --- /dev/null +++ b/src/mainboard/via/epia-m850/Kconfig @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011-2012 Alexandru Gagniuc +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +if BOARD_VIA_EPIA_M850 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_VIA_NANO + select NORTHBRIDGE_VIA_VX900 + select SUPERIO_FINTEK_F81865F + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select HAVE_MP_TABLE + #select HAVE_OPTION_TABLE + #select HAVE_ACPI_TABLES + #select HAVE_ACPI_RESUME + #select BOARD_HAS_FADT + select BOARD_ROMSIZE_KB_512 + +config MAINBOARD_DIR + string + default via/epia-m850 + +config MAINBOARD_PART_NUMBER + string + default "EPIA-M850" + +config IRQ_SLOT_COUNT + int + default 13 + +endif # BOARD_VIA_EPIA_M850 diff --git a/src/mainboard/via/epia-m850/Makefile.inc b/src/mainboard/via/epia-m850/Makefile.inc new file mode 100644 index 0000000000..9c6d31f3ff --- /dev/null +++ b/src/mainboard/via/epia-m850/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +#romstage-y += ./../../../superio/fintek/f81865f/f81865f_early_serial.c + diff --git a/src/mainboard/via/epia-m850/devicetree.cb b/src/mainboard/via/epia-m850/devicetree.cb new file mode 100644 index 0000000000..0c21cc8f58 --- /dev/null +++ b/src/mainboard/via/epia-m850/devicetree.cb @@ -0,0 +1,111 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011-2013 Alexandru Gagniuc +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see . +## + +chip northbridge/via/vx900 # Northbridge + register "assign_pex_to_dp" = "0" + register "pcie_port1_2_lane_wide" = "1" + register "ext_int_route_to_pirq" = "'H'" + + device cpu_cluster 0 on # APIC cluster + chip cpu/via/nano # VIA NANO + device lapic 0 on end # APIC + end + end + device domain 0 on + device pci 0.0 on end # [0410] Host controller + device pci 0.1 on end # [1410] Error Reporting + device pci 0.2 on end # [2410] CPU Bus Control + device pci 0.3 on end # [3410] DRAM Bus Control + device pci 0.4 on end # [4410] Power Management + device pci 0.5 on # [5410] APIC+Traffic Control + chip drivers/generic/ioapic + register "have_isa_interrupts" = "0" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "0xfecc0000" + device ioapic 2 on end + end + end + device pci 0.6 off end # [6410] Scratch Registers + device pci 0.7 on end # [7410] V4 Link Control + device pci 1.0 on # [7122] VGA Chrome9 HD + ioapic_irq 2 INTA 0x28 + end + device pci 1.1 on # [9170] Audio Device + ioapic_irq 2 INTA 0x29 + end + device pci 3.0 on end # [a410] PEX1 + device pci 3.1 on end # [b410] PEX2 + device pci 3.2 on end # [c410] PEX3 + device pci 3.3 on end # [d410] PEX4 + device pci 3.4 on end # [e410] PCIE bridge + device pci b.0 on end # [a409] USB Device + device pci c.0 off end # [95d0] SDIO Host Controller + device pci d.0 off end # [9530] Memory Card controller + device pci f.0 on # [9001] SATA Controller + ioapic_irq 1 INTA 0x15 + end + device pci 10.0 on end # [3038] USB 1.1 + device pci 10.1 on end # [3038] USB 1.1 + device pci 10.2 on end # [3038] USB 1.1 + device pci 10.3 on end # [3038] USB 1.1 + device pci 10.4 on end # [3104] USB 2.0 + device pci 11.0 on # [8410] LPC Bus Control + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "0xfec00000" + device ioapic 1 on end + end + #chip drivers/generic/generic # DIMM 0 channel 1 + # device i2c 50 on end + #end + #chip drivers/generic/generic # DIMM 1 channel 1 + # device i2c 51 on end + #end + chip superio/fintek/f81865f # Super duper IO + device pnp 4e.0 off end # Floppy + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 off end # Keyboard not here + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.12 on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 10 + end + device pnp 4e.13 on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 11 + end + end # superio/fintek/f81865f + end # LPC + device pci 11.7 on end # [a353] North-South control + device pci 14.0 on end # [3288] Azalia HDAC + end +end diff --git a/src/mainboard/via/epia-m850/irq_tables.c b/src/mainboard/via/epia-m850/irq_tables.c new file mode 100644 index 0000000000..28fbb4f21a --- /dev/null +++ b/src/mainboard/via/epia-m850/irq_tables.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include /* <- For memset */ + +#define _OFF 0x00 +#define ___OFF 0x0000 +#define LNKA 1 +#define LNKB 2 +#define LNKC 3 +#define LNKD 4 +#define LNKE 5 +#define LNKF 6 +#define LNKG 7 +#define LNKH 8 +#define BITMAP 0xdce0 +/* The link that carries the SATA interrupt has its own mask, just in case + * we want to make sure our SATA controller gets mapped to IRQ 14 */ +#define B_SATA BITMAP + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 13, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x11 << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively for PCI */ + PCI_VENDOR_ID_VIA, /* Vendor */ + PCI_DEVICE_ID_VIA_VX900_LPC, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x19, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, + {0x00, (0x03 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0}, + {0x00, (0x0a << 3) | 0x0, {{LNKA, BITMAP}, {LNKB, B_SATA}, {LNKC, BITMAP}, {LNKD, BITMAP}}, 0x0, 0x0}, + {0x00, (0x0b << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, + {0x00, (0x0c << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, + {0x00, (0x0d << 3) | 0x0, {{LNKA, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, + {0x00, (0x0f << 3) | 0x0, {{LNKB, B_SATA}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, + {0x00, (0x10 << 3) | 0x0, {{LNKA, BITMAP}, {LNKB, B_SATA}, {LNKC, BITMAP}, {LNKD, BITMAP}}, 0x0, 0x0}, + {0x00, (0x14 << 3) | 0x0, {{LNKB, B_SATA}, {_OFF, ___OFF}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, + {0x01, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x1, 0x0}, + {0x02, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x2, 0x0}, + {0x03, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0}, + {0x04, (0x00 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c new file mode 100644 index 0000000000..dbe682cfce --- /dev/null +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include + +#if CONFIG_VGA_ROM_RUN + +#include +#include + +#include + +static int vx900_int15_handler(void) +{ + int res; + + printk(BIOS_DEBUG, "%s %0x\n", __func__, X86_AX & 0xffff); + /* Set AX return value here so we don't set it every time. Just set it + * to something else if the callback is unsupported */ + res = -1; + switch (X86_AX & 0xffff) { +#if 0 + case 0x5f01: + /* VGA POST - panel type */ + /* FIXME: Don't hardcode panel type */ + /* Panel Type Number */ + X86_CX = 0; + res = 0; + break; + case 0x5f02: + { + /* Boot device selection */ + X86_BL = INT15_5F02_BL_HWOPT_CRTCONN; + /* FIXME: or 0 ? */ + X86_BH = 0; // INT15_5F02_BH_TV_CONN_DEFAULT; + X86_EBX = 0; // INT15_5F02_EBX_HDTV_RGB; + X86_ECX = INT15_5F02_ECX_DISPLAY_CRT; + //X86_ECX |= INT15_5F02_ECX_TV_MODE_RGB; + //X86_ECX |= INT15_5F02_ECX_HDTV_1080P; + X86_DL = INT15_5F02_DL_TV_LAYOUT_DEFAULT; + res = 0; + break; + } +#endif + case 0x5f18: + X86_BL = vx900_int15_get_5f18_bl(); + res = 0; + break; +#if 0 + case 0x5f2a: + /* Get SSC Control Settings */ + /* FIXME: No idea what this does. Just disable this feature + * for now */ + X86_CX = INT15_5F2A_CX_SSC_ENABLE; + res = 0; + break; + case 0x5f2b: + /* Engine clock setting */ + /* FIXME: ECLK fixed 250MHz ? */ + X86_EBX = INT15_5F2B_EBX_ECLK_250MHZ; + break; +#endif + default: + printk(BIOS_DEBUG, "Unsupported INT15 call %04x!\n", + X86_AX & 0xffff); + X86_AX = 0; + res = -1; + break; + } + + if (res == 0) + X86_AX = 0x5f; + else + X86_AX = 0; + return X86_AX; +} +#endif + +static void mainboard_enable(device_t dev) +{ + (void)dev; + +#if CONFIG_VGA_ROM_RUN + print_debug("Installing INT15 handler...\n"); + mainboard_interrupt_handlers(0x15, &vx900_int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("VIA EPIA-M850 Mainboard") + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c new file mode 100644 index 0000000000..364de4844b --- /dev/null +++ b/src/mainboard/via/epia-m850/romstage.c @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 Alexandru Gagniuc + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Inspired from the EPIA-M700 + */ +#undef CONFIG_COLLECT_TIMESTAMPS +#define CONFIG_COLLECT_TIMESTAMPS 1 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "northbridge/via/vx900/early_vx900.h" +#include "northbridge/via/vx900/raminit.h" +/* FIXME: This is the only .c include we couldn't get rid of */ +#include "superio/fintek/f81865f/f81865f_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x4e, 0x10) + +static inline u64 tsc2u64(tsc_t tsc) +{ + return ((u64) tsc.hi << 32) | tsc.lo; +} + +/* FIXME: This board comes in two flavours. This is for the faster CPU, but + * will probably not be correct for the other CPU */ +#define TSC_PER_USEC 1297 +static inline u32 tsc2ms(u64 end, u64 start) +{ + return ((u32) (end - start) / TSC_PER_USEC) / 1000; +} + +/* cache_as_ram.inc jumps to here. */ +void main(unsigned long bist) +{ + u32 tolm; + u64 start, end; + tsc_t tsc_at_romstage_start = rdtsc(); + + /* First thing we need to do on the VX900, before anything else */ + vx900_enable_pci_config_space(); + + /* Serial console is easy to take care of */ + f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + print_debug("Console initialized. \n"); + + vx900_cpu_bus_interface_setup(); + + /* Be smart. Get this info */ + vx900_print_strapping_info(); + /* DEVEL helper */ + vx900_disable_auto_reboot(); + /* Halt if there was a built-in self test failure. */ + report_bist_failure(bist); + + /* Oh, almighty, give us the SMBUS */ + enable_smbus(); + + tsc_t tsc_before_raminit = rdtsc(); + /* Now we can worry about raminit. + * This board only has DDR3, so no need to worry about which DRAM type + * to use */ + dimm_layout dimms = { {0x50, 0x51, SPD_END_LIST} }; + vx900_init_dram_ddr3(&dimms); + tsc_t tsc_after_raminit = rdtsc(); + + /* TODO: All these ram_checks are here to ensure we test most of the RAM + * below 4G. They should not be needed once VX900 raminit is stable */ + ram_check(0, 0x80); + ram_check(512 << 10, 0x80); + ram_check((1 << 20) - (1 << 10), 0x80); + ram_check((1 << 24), 0x80); + ram_check((512 + 256 - 1) << 20, 0x80); + ram_check(0x80c0000, 0x80); + tolm = ((pci_read_config16(MCU, 0x84) & 0xfff0) >> 4) << 20; + if (tolm > (1 * (u32) GiB)) + ram_check(1024 << 10, 0x80); + if (tolm > (2 * (u32) GiB)) + ram_check(2048 << 20, 0x80); + + print_debug("We passed RAM verify\n"); +#ifdef GONFIG_EARLY_CBMEM_INIT + /* We got RAM working, now we can write the timestamps to RAM */ + cbmem_initialize(); + timestamp_init(tsc_at_romstage_start); + timestamp_add(TS_START_ROMSTAGE, tsc_at_romstage_start); + timestamp_add(TS_BEFORE_INITRAM, tsc_before_raminit); + timestamp_add(TS_AFTER_INITRAM, tsc_after_raminit); + timestamp_add_now(TS_END_ROMSTAGE); +#endif + /* FIXME: See if this is needed or take this out please */ + /* Disable Memcard and SDIO */ + pci_mod_config8(LPC, 0x51, 0, (1 << 7) | (1 << 4)); + + /* Informative character. Could be removed at a later time. */ + start = tsc2u64(tsc_at_romstage_start); + end = tsc2u64(tsc_before_raminit); + printk(BIOS_INFO, "Before raminit %ums\n", tsc2ms(end, start)); + + start = end; + end = tsc2u64(tsc_after_raminit); + printk(BIOS_INFO, "Actual Raminit %ums\n", tsc2ms(end, start)); +} -- cgit v1.2.3