From 39648bb54b2bdeda3bc5a1bd63b8b5f60478f2f7 Mon Sep 17 00:00:00 2001 From: Pratik Prajapati Date: Thu, 24 Aug 2017 17:35:55 -0700 Subject: mainboard/intel/cannonlake_rvp: SMBus, SAGV and Skip FSP MPInit in devicetree Set SMBus, SAGV and Skip FSP MPInit configuration from devicetree.cb Change-Id: Ic810b003bf7fb13447d5d5dcd49cfcc31785b440 Signed-off-by: Pratik Prajapati Reviewed-on: https://review.coreboot.org/21198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 5 +++++ src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'src') diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index e71f15b8cf..a3c4c80d14 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -4,6 +4,11 @@ chip soc/intel/cannonlake device lapic 0 on end end + # FSP configuration + register "SaGv" = "3" + register "FspSkipMpInit" = "1" + register "SmbusEnable" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index e71f15b8cf..a3c4c80d14 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -4,6 +4,11 @@ chip soc/intel/cannonlake device lapic 0 on end end + # FSP configuration + register "SaGv" = "3" + register "FspSkipMpInit" = "1" + register "SmbusEnable" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- cgit v1.2.3