From 3f559d960c637f09f74bbe217c562498ca1a5311 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 30 Jan 2019 18:44:09 +0530 Subject: soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ix TEST=Dump SSDT entries to verify _CST between S0ix enable and disable. >> iasl -d SSDT # to generate SSDT.dsl Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/31153 Tested-by: build bot (Jenkins) Reviewed-by: Ronak Kanabar Reviewed-by: Aamir Bohra Reviewed-by: Paul Menzel --- src/soc/intel/icelake/acpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 39ec58a954..0e13d0340a 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -119,13 +119,13 @@ static const acpi_cstate_t cstate_map[NUM_C_STATES] = { }, }; -static int cstate_set_s0ix[] = { +static int cstate_set_non_s0ix[] = { C_STATE_C1E, C_STATE_C6_LONG_LAT, C_STATE_C7S_LONG_LAT }; -static int cstate_set_non_s0ix[] = { +static int cstate_set_s0ix[] = { C_STATE_C1E, C_STATE_C7S_LONG_LAT, C_STATE_C10 -- cgit v1.2.3