From 4318a978a7a7ded371cdb3faf88b70fb99cbdb41 Mon Sep 17 00:00:00 2001
From: Jacob Garber <jgarber1@ualberta.ca>
Date: Wed, 3 Apr 2019 15:46:24 -0600
Subject: vc/amd/agesa/f14: Add missing break statement
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

We do not want to ASSERT(FALSE).

Found-by: Coverity Scan, CID 1241850 (MISSING_BREAK)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ia08bb519cdb5ef5d2a79898706c7fac7e58adf3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
index 7fb195d4bc..daf529c367 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
@@ -792,6 +792,7 @@ MemNS3GetSetBitField (
         break;
       case AccessS3SaveWidth32:
         RegValue = *(UINT32 *) Value;
+	break;
       default:
         ASSERT (FALSE);
       }
-- 
cgit v1.2.3