From 433acc2d3d6cfb3d16030cbba7be9a5defccf057 Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Fri, 22 Nov 2019 12:00:24 +0800 Subject: soc/mediatek/mt8183: disable BBLPM of DCXO core When we only enable XO_SOC and mask most BBLPM requests, the BBLPM HW arbiter will have DCXO core to enter Baseband Low-Power Mode(BBLPM). Under BBLPM mode, inaccurate(about 1.5KHz offset) 26MHz clocks from crystal is provided and crystal voltage will drop from 1.8V to 0.7V or lower. In order to ensure the stability by always outputting an accuarate system clock when system is running. We should disable BBLPM when only XO_SOC enabled. BRANCH=kukui TEST=accurate 26MHz provided and correct crystal voltage swing Change-Id: Iea72a964507a19735cf92e3774cd8a94c06545b2 Signed-off-by: Weiyi Lu Reviewed-on: https://review.coreboot.org/c/coreboot/+/37136 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8183/rtc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 19b717cc82..6e17a309fe 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -435,8 +435,8 @@ void mt6358_dcxo_disable_unused(void) { /* Disable clock buffer XO_CEL */ rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800); - /* Mask bblpm */ - rtc_write(PMIC_RG_DCXO_CW23, 0x0053); + /* Mask bblpm request and switch off bblpm mode */ + rtc_write(PMIC_RG_DCXO_CW23, 0x0052); } /* the rtc boot flow entry */ -- cgit v1.2.3