From 438f86166325e4f8089be5c65b40075d77a0406c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 7 Jan 2019 11:25:29 +0100 Subject: src/mb/asus/p5qpl-am/romstage.c: Fix comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I2b3ad53766bc9cef5ae00392814a03a3e177ad35 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/30705 Reviewed-by: Kyösti Mälkki Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/asus/p5qpl-am/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index bc04261848..96473bbcc5 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -54,7 +54,7 @@ static u8 msr_get_fsb(void) } /* - * BSEL mch straps are not hooked up to the CPU as usual but the the SIO + * BSEL MCH straps are not hooked up to the CPU as usual but to the SIO * BSEL0 -> not hooked up (such configs are not supported anyways) * BSEL1 -> GPIO33 * BSEL2 -> GPIO40 -- cgit v1.2.3