From 448e5a2810aa735e0a062296b79db8efce559631 Mon Sep 17 00:00:00 2001
From: Shobhit Srivastava <shobhit.srivastava@intel.com>
Date: Fri, 9 Oct 2015 17:05:16 +0530
Subject: google/cyan: Enable CA Mirror

Cherry-pick from Chromium commit e49deb1.

Configuring UPD PcdCaMirrorEn. This is a board specific parameter.
CA mirror is the Command Address mirroring option that is board
specific.

Original-Change-Id: I05174e18d650332d838e5036c713e91c4840ee75
Original-Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>

Change-Id: Ibd0c811d41cb592634f7785edb83ad2f423546c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/mainboard/google/cyan/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb
index 2f2b2df7de..0454650c68 100644
--- a/src/mainboard/google/cyan/devicetree.cb
+++ b/src/mainboard/google/cyan/devicetree.cb
@@ -13,6 +13,7 @@ chip soc/intel/braswell
 	register "PcdApertureSize" = "2"
 	register "PcdGttSize" = "1"
 	register "PcdDvfsEnable" = "1"
+	register "PcdCaMirrorEn" = "0"
 
 	############################################################
 	# Set the parameters for SiliconInit
-- 
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