From 4520aa2891263736791861c1fa12dd8f0c34a19e Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 23 Apr 2021 11:42:19 -0600 Subject: soc/amd/common/acp: Move Audio Co-processor driver to common Audio Co-processor driver is similar for both Picasso and Cezanne SoCs. Hence move it to the common location. BUG=None. TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards. Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/mainboard/amd/bilby/devicetree.cb | 3 +- .../amd/mandolin/variants/cereme/devicetree.cb | 3 +- .../amd/mandolin/variants/mandolin/devicetree.cb | 3 +- .../zork/variants/baseboard/devicetree_dalboz.cb | 9 ++- .../zork/variants/baseboard/devicetree_trembyle.cb | 9 ++- .../zork/variants/baseboard/ramstage_common.c | 4 +- .../google/zork/variants/vilboz/variant.c | 2 +- src/soc/amd/common/block/acp/Kconfig | 4 ++ src/soc/amd/common/block/acp/Makefile.inc | 1 + src/soc/amd/common/block/acp/acp.c | 70 ++++++++++++++++++++++ src/soc/amd/common/block/include/amdblocks/acp.h | 25 ++++++++ src/soc/amd/common/block/include/amdblocks/chip.h | 4 ++ src/soc/amd/picasso/Kconfig | 1 + src/soc/amd/picasso/Makefile.inc | 1 - src/soc/amd/picasso/acp.c | 67 --------------------- src/soc/amd/picasso/chip.h | 15 ----- src/soc/amd/picasso/fch.c | 6 +- src/soc/amd/picasso/include/soc/acp.h | 14 ----- 18 files changed, 129 insertions(+), 112 deletions(-) create mode 100644 src/soc/amd/common/block/acp/Kconfig create mode 100644 src/soc/amd/common/block/acp/Makefile.inc create mode 100644 src/soc/amd/common/block/acp/acp.c create mode 100644 src/soc/amd/common/block/include/amdblocks/acp.h delete mode 100644 src/soc/amd/picasso/acp.c delete mode 100644 src/soc/amd/picasso/include/soc/acp.h (limited to 'src') diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index c07415e94c..5429234d6c 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/picasso - register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" + # ACP Configuration + register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_MAX_HDA" # Set FADT Configuration register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index addb328ba4..c02cb8a448 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/picasso - register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" + # ACP Configuration + register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_MAX_HDA" # Set FADT Configuration register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index f4f178a3d3..1a86ab7ce9 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/amd/picasso - register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" + # ACP Configuration + register "common_config.acp_config.acp_pin_cfg" = "I2S_PINS_MAX_HDA" # Set FADT Configuration register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 3f4c4047e9..f0fcf37c26 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -13,9 +13,12 @@ chip soc/amd/picasso # See table 5-34 ACPI 6.3 spec register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" - register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" - register "acp_i2s_wake_enable" = "0" - register "acp_pme_enable" = "0" + # ACP Configuration + register "common_config.acp_config" = "{ + .acp_pin_cfg = I2S_PINS_I2S_TDM, + .acp_i2s_wake_enable = 0, + .acp_pme_enable = 0, + }" # Start : OPN Performance Configuration # (Configuratin that is common for all variants) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 3270b6f954..ececa3e050 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -6,9 +6,12 @@ chip soc/amd/picasso # See table 5-34 ACPI 6.3 spec register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" - register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" - register "acp_i2s_wake_enable" = "0" - register "acp_pme_enable" = "0" + # ACP Configuration + register "common_config.acp_config" = "{ + .acp_pin_cfg = I2S_PINS_I2S_TDM, + .acp_i2s_wake_enable = 0, + .acp_pme_enable = 0, + }" # Start : OPN Performance Configuration # (Configuratin that is common for all variants) diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c index a9414b92e0..f7b8ed4253 100644 --- a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c +++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c @@ -70,8 +70,8 @@ static void update_hp_int_odl(void) * need to be set to trigger I2S_WAKE event for headphone jack. */ soc_cfg = config_of_soc(); - soc_cfg->acp_i2s_wake_enable = 1; - soc_cfg->acp_pme_enable = 1; + soc_cfg->common_config.acp_config.acp_i2s_wake_enable = 1; + soc_cfg->common_config.acp_config.acp_pme_enable = 1; } static void update_dmic_gpio(void) diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index 43ca0e51df..df82698b66 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -45,7 +45,7 @@ void variant_devtree_update(void) /* b:/174121847 Use external OSC to mitigate noise for WWAN sku. */ if (variant_has_wwan()) { - soc_cfg->acp_i2s_use_external_48mhz_osc = 1; + soc_cfg->common_config.acp_config.acp_i2s_use_external_48mhz_osc = 1; /* eDP phy tuning settings */ soc_cfg->edp_phy_override = ENABLE_EDP_TUNINGSET; diff --git a/src/soc/amd/common/block/acp/Kconfig b/src/soc/amd/common/block/acp/Kconfig new file mode 100644 index 0000000000..ca733cd5de --- /dev/null +++ b/src/soc/amd/common/block/acp/Kconfig @@ -0,0 +1,4 @@ +config SOC_AMD_COMMON_BLOCK_ACP + bool + help + Select this option to perform Audio Co-Processor(ACP) configuration. diff --git a/src/soc/amd/common/block/acp/Makefile.inc b/src/soc/amd/common/block/acp/Makefile.inc new file mode 100644 index 0000000000..cdff5bdb76 --- /dev/null +++ b/src/soc/amd/common/block/acp/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP) += acp.c diff --git a/src/soc/amd/common/block/acp/acp.c b/src/soc/amd/common/block/acp/acp.c new file mode 100644 index 0000000000..3cb7c453c8 --- /dev/null +++ b/src/soc/amd/common/block/acp/acp.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* ACP registers and associated fields */ +#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ +#define PIN_CONFIG_MASK (7 << 0) +#define ACP_I2S_WAKE_EN 0x1414 +#define WAKE_EN_MASK (1 << 0) +#define ACP_PME_EN 0x1418 +#define PME_EN_MASK (1 << 0) + +static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set) +{ + clrsetbits32((void *)(bar + reg), clear, set); +} + +static void init(struct device *dev) +{ + const struct soc_amd_common_config *cfg = soc_get_common_config(); + struct resource *res; + uintptr_t bar; + + res = dev->resource_list; + if (!res || !res->base) { + printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__); + return; + } + + /* Set the proper I2S_PIN_CONFIG state */ + bar = (uintptr_t)res->base; + acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_config.acp_pin_cfg); + + /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ + acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_config.acp_i2s_wake_enable); + acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_config.acp_pme_enable); +} + +static const char *acp_acpi_name(const struct device *dev) +{ + return "ACPD"; +} + +static struct device_operations acp_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = init, + .ops_pci = &pci_dev_ops_pci, + .scan_bus = scan_static_bus, + .acpi_name = acp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; + +static const struct pci_driver acp_driver __pci_driver = { + .ops = &acp_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_FAM17H_ACP, +}; diff --git a/src/soc/amd/common/block/include/amdblocks/acp.h b/src/soc/amd/common/block/include/amdblocks/acp.h new file mode 100644 index 0000000000..f091c0540f --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/acp.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_COMMON_ACP_H +#define AMD_COMMON_ACP_H + +struct acp_config { + enum { + I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */ + I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */ + I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */ + I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */ + I2S_PINS_I2S_TDM = 4, + I2S_PINS_UNCONF = 7, /* All pads will be input mode */ + } acp_pin_cfg; + + /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */ + u8 acp_i2s_wake_enable; + /* Enable ACP PME (0 = disable, 1 = enable) */ + u8 acp_pme_enable; + + /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ + bool acp_i2s_use_external_48mhz_osc; +}; + +#endif /* AMD_COMMON_ACP_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index b06ff85d11..c80a6746e0 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -5,6 +5,7 @@ #include #include +#include #include struct soc_amd_common_config { @@ -36,6 +37,9 @@ struct soc_amd_common_config { /* See MP_IRQ_* from mpspec.h */ uint8_t flags; } irq_override[16]; + + /* Audio Co-processor (ACP) configuration */ + struct acp_config acp_config; }; /* diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 0c494d9c1c..2f36f2e4ab 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select HAVE_EM100_SUPPORT select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_ACP select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_GPIO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 081a65fac2..b5154a40f5 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -43,7 +43,6 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c ramstage-y += gpio.c ramstage-y += fch.c ramstage-y += reset.c -ramstage-y += acp.c ramstage-y += sata.c ramstage-y += uart.c ramstage-y += soc_util.c diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c deleted file mode 100644 index d1ae21cec4..0000000000 --- a/src/soc/amd/picasso/acp.c +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" -#include -#include -#include -#include -#include -#include - -static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set) -{ - clrsetbits32((void *)(bar + reg), clear, set); -} - -static void init(struct device *dev) -{ - const struct soc_amd_picasso_config *cfg; - struct resource *res; - uintptr_t bar; - - /* Set the proper I2S_PIN_CONFIG state */ - cfg = config_of_soc(); - - res = dev->resource_list; - if (!res || !res->base) { - printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__); - return; - } - - bar = (uintptr_t)res->base; - acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_pin_cfg); - - /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ - acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_i2s_wake_enable); - acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_pme_enable); -} - -static const char *acp_acpi_name(const struct device *dev) -{ - return "ACPD"; -} - -static struct device_operations acp_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = init, - .ops_pci = &pci_dev_ops_pci, - .scan_bus = scan_static_bus, - .acpi_name = acp_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, -}; - -static const struct pci_driver acp_driver __pci_driver = { - .ops = &acp_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_FAM17H_ACP, -}; diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index e84db3561e..d59a4c8207 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -105,19 +105,6 @@ struct soc_amd_picasso_config { */ u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; - enum { - I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */ - I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */ - I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */ - I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */ - I2S_PINS_I2S_TDM = 4, - I2S_PINS_UNCONF = 7, /* All pads will be input mode */ - } acp_pin_cfg; - - /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */ - u8 acp_i2s_wake_enable; - /* Enable ACP PME (0 = disable, 1 = enable) */ - u8 acp_pme_enable; /* System config index */ uint8_t system_config; @@ -270,8 +257,6 @@ struct soc_amd_picasso_config { /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; - /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ - bool acp_i2s_use_external_48mhz_osc; /* eDP phy tuning settings */ uint16_t edp_phy_override; diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index b65bc6fbe1..a871ccf9cb 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -90,12 +90,12 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) void sb_clk_output_48Mhz(void) { u32 ctrl; - const struct soc_amd_picasso_config *cfg; - cfg = config_of_soc(); + const struct soc_amd_common_config *cfg = soc_get_common_config(); ctrl = misc_read32(MISC_CLK_CNTL1); /* If used external clock source for I2S, disable the internal clock output */ - if (cfg->acp_i2s_use_external_48mhz_osc && cfg->acp_pin_cfg == I2S_PINS_I2S_TDM) + if (cfg->acp_config.acp_i2s_use_external_48mhz_osc && + cfg->acp_config.acp_pin_cfg == I2S_PINS_I2S_TDM) ctrl &= ~BP_X48M0_OUTPUT_EN; else ctrl |= BP_X48M0_OUTPUT_EN; diff --git a/src/soc/amd/picasso/include/soc/acp.h b/src/soc/amd/picasso/include/soc/acp.h deleted file mode 100644 index f812b32a98..0000000000 --- a/src/soc/amd/picasso/include/soc/acp.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef AMD_PICASSO_ACP_H -#define AMD_PICASSO_ACP_H - -/* Bus A D0F5 - Audio Processor */ -#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ -#define PIN_CONFIG_MASK (7 << 0) -#define ACP_I2S_WAKE_EN 0x1414 -#define WAKE_EN_MASK (1 << 0) -#define ACP_PME_EN 0x1418 -#define PME_EN_MASK (1 << 0) - -#endif /* AMD_PICASSO_ACP_H */ -- cgit v1.2.3