From 468d02cc82151366a2781c9af29e6737105495cb Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Wed, 23 Oct 2019 21:44:42 -0600 Subject: src/[northbridge,security]: change "unsigned" to "unsigned int" Signed-off-by: Martin Roth Change-Id: If6b5930f78c3da6dcefaa7b6202cd0424a24525b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/amdfam10/early_ht.c | 8 +-- src/northbridge/amd/amdfam10/northbridge.c | 42 ++++++++-------- src/northbridge/amd/amdk8/amdk8.h | 2 +- src/northbridge/amd/amdmct/mct/mct.h | 14 +++--- src/northbridge/amd/pi/00630F01/northbridge.c | 4 +- src/northbridge/amd/pi/00660F01/northbridge.c | 32 ++++++------ src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- src/northbridge/intel/e7505/raminit.c | 4 +- src/northbridge/intel/gm45/raminit.c | 2 +- .../intel/gm45/raminit_read_write_training.c | 2 +- src/northbridge/intel/haswell/gma.c | 2 +- src/northbridge/intel/i440bx/debug.c | 4 +- src/northbridge/intel/i440bx/raminit.h | 2 +- src/northbridge/intel/nehalem/gma.c | 2 +- src/northbridge/intel/nehalem/northbridge.c | 2 +- src/northbridge/intel/nehalem/raminit.c | 58 +++++++++++----------- src/security/vboot/vbnv.c | 2 +- 19 files changed, 94 insertions(+), 94 deletions(-) (limited to 'src') diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c6457a3998..01aedab94d 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -645,7 +645,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 928d9d2e8a..a05125593b 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -661,7 +661,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 3f2b138533..dc0f6840e2 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -50,11 +50,11 @@ void enumerate_ht_chain(void) * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ - unsigned next_unitid, last_unitid = 0; + unsigned int next_unitid, last_unitid = 0; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 // let't record the device of last ht device, So we can set the // Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE - unsigned real_last_unitid = 0; + unsigned int real_last_unitid = 0; u8 real_last_pos = 0; int ht_dev_num = 0; // except host_bridge u8 end_used = 0; @@ -96,8 +96,8 @@ void enumerate_ht_chain(void) pci_io_write_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS, flags); flags = pci_io_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); if ((flags >> 13) == 0) { - unsigned count; - unsigned ctrl, ctrl_off; + unsigned int count; + unsigned int ctrl, ctrl_off; pci_devfn_t devx; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 79f43db387..df1d947cdb 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -62,7 +62,7 @@ static struct device *__f0_dev[FX_DEVS]; struct device *__f1_dev[FX_DEVS]; static struct device *__f2_dev[FX_DEVS]; static struct device *__f4_dev[FX_DEVS]; -static unsigned fx_devs = 0; +static unsigned int fx_devs = 0; struct device *get_node_pci(u32 nodeid, u32 fn) { @@ -94,14 +94,14 @@ static void get_fx_devs(void) } } -static u32 f1_read_config32(unsigned reg) +static u32 f1_read_config32(unsigned int reg) { if (fx_devs == 0) get_fx_devs(); return pci_read_config32(__f1_dev[0], reg); } -static void f1_write_config32(unsigned reg, u32 value) +static void f1_write_config32(unsigned int reg, u32 value) { int i; if (fx_devs == 0) @@ -118,7 +118,7 @@ static void f1_write_config32(unsigned reg, u32 value) u32 amdfam10_nodeid(struct device *dev) { #if NODE_NUMS == 64 - unsigned busn; + unsigned int busn; busn = dev->bus->secondary; if (busn != CONFIG_CBB) { return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; @@ -361,11 +361,11 @@ static void amdfam10_scan_chains(struct device *dev) } -static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, - unsigned goal_link) +static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, + unsigned int goal_link) { struct resource *res; - unsigned nodeid, link = 0; + unsigned int nodeid, link = 0; int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { @@ -389,7 +389,7 @@ static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_node return result; } -static struct resource *amdfam10_find_iopair(struct device *dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link) { struct resource *resource; u32 free_reg, reg; @@ -514,7 +514,7 @@ static void amdfam10_set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; - unsigned reg, link_num; + unsigned int reg, link_num; char buf[50]; /* Make certain the resource has actually been set */ @@ -564,7 +564,7 @@ static void amdfam10_set_resource(struct device *dev, struct resource *resource, * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device *dev, unsigned int nodeid) { struct bus *link; struct resource *res; @@ -607,7 +607,7 @@ static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid) static void amdfam10_set_resources(struct device *dev) { - unsigned nodeid; + unsigned int nodeid; struct bus *bus; struct resource *res; @@ -685,7 +685,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = { static void amdfam10_domain_read_resources(struct device *dev) { - unsigned reg; + unsigned int reg; uint8_t nvram; uint8_t enable_cc6; @@ -697,7 +697,7 @@ static void amdfam10_domain_read_resources(struct device *dev) limit = f1_read_config32(reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { - unsigned nodeid, reg_link; + unsigned int nodeid, reg_link; struct device *reg_dev; if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); @@ -817,7 +817,7 @@ static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { - unsigned hole_startk; + unsigned int hole_startk; int node_id; }; @@ -857,7 +857,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } @@ -949,7 +949,7 @@ static void amdfam10_domain_set_resources(struct device *dev) /* split the region to accommodate pci memory space */ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { - unsigned pre_sizek; + unsigned int pre_sizek; pre_sizek = mmio_basek - basek; if (pre_sizek > 0) { ram_resource(dev, (idx | i), basek, pre_sizek); @@ -1325,7 +1325,7 @@ static void sysconf_init(struct device *dev) // first node sysconf.segbit = 0; sysconf.ht_c_num = 0; - unsigned ht_c_index; + unsigned int ht_c_index; for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) { sysconf.ht_c_conf_bus[ht_c_index] = 0; @@ -1386,12 +1386,12 @@ static void cpu_bus_scan(struct device *dev) int nvram = 0; int i,j; int nodes; - unsigned nb_cfg_54; - unsigned siblings; + unsigned int nb_cfg_54; + unsigned int siblings; int cores_found; int disable_siblings; uint8_t disable_cu_siblings = 0; - unsigned ApicIdCoreIdSize; + unsigned int ApicIdCoreIdSize; nb_cfg_54 = 0; ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf); @@ -1485,7 +1485,7 @@ static void cpu_bus_scan(struct device *dev) for (i = 0; i < nodes; i++) { struct device *cdb_dev; - unsigned busn, devn; + unsigned int busn, devn; struct bus *pbus; uint8_t fam15h = 0; diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index d8cbc36ff8..2b821b7c9e 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -26,6 +26,6 @@ void set_bios_reset(void); void distinguish_cpu_resets(unsigned int nodeid); unsigned int get_sblk(void); -unsigned int get_sbbusn(unsigned sblk); +unsigned int get_sbbusn(unsigned int sblk); #endif /* AMDK8_H */ diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h index d13c42cdb5..598ab37e76 100644 --- a/src/northbridge/amd/amdmct/mct/mct.h +++ b/src/northbridge/amd/amdmct/mct/mct.h @@ -508,12 +508,12 @@ void K8FInterleaveBanks(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT void mctInitWithWritetoCS(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); void mctGet_PS_Cfg(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -void Get_ChannelPS_Cfg0(unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned DATAAload, - unsigned *AddrTmgCTL, unsigned *ODC_CTL); -void Get_ChannelPS_Cfg1(unsigned MAAdimms, unsigned Speed, unsigned MAAload, - unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val); -void Get_ChannelPS_Cfg2(unsigned MAAdimms, unsigned Speed, unsigned MAAload, - unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val); +void Get_ChannelPS_Cfg0(unsigned int MAAdimms, unsigned int Speed, unsigned int MAAload, unsigned int DATAAload, + unsigned int *AddrTmgCTL, unsigned int *ODC_CTL); +void Get_ChannelPS_Cfg1(unsigned int MAAdimms, unsigned int Speed, unsigned int MAAload, + unsigned int *AddrTmgCTL, unsigned int *ODC_CTL, unsigned int *val); +void Get_ChannelPS_Cfg2(unsigned int MAAdimms, unsigned int Speed, unsigned int MAAload, + unsigned int *AddrTmgCTL, unsigned int *ODC_CTL, unsigned int *val); u8 MCTDefRet(void); @@ -532,7 +532,7 @@ void K8FCPUMemTyping(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTsta void K8FCPUMemTyping_clear(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void K8FWaitMemClrDelay(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -unsigned K8FCalcFinalDQSRcvValue(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, unsigned LeftRcvEn, unsigned RightRcvEn, unsigned *valid); +unsigned int K8FCalcFinalDQSRcvValue(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, unsigned int LeftRcvEn, unsigned int RightRcvEn, unsigned int *valid); void K8FGetDeltaTSCPart1(struct DCTStatStruc *pDCTstat); void K8FGetDeltaTSCPart2(struct DCTStatStruc *pDCTstat); diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 518c6e2ab9..40d3e0577c 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -314,7 +314,7 @@ static void read_resources(struct device *dev) static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; - unsigned reg, link_num; + unsigned int reg, link_num; char buf[50]; /* Make certain the resource has actually been set */ @@ -658,7 +658,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G mem_hole.node_id = i; break; //only one hole } diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index c67e5ff2ee..533b651427 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -47,13 +47,13 @@ typedef struct dram_base_mask { u32 mask; //[47:27] at [28:8] and enable at bit 0 } dram_base_mask_t; -static unsigned node_nums; -static unsigned sblink; +static unsigned int node_nums; +static unsigned int sblink; static struct device *__f0_dev[MAX_NODE_NUMS]; static struct device *__f1_dev[MAX_NODE_NUMS]; static struct device *__f2_dev[MAX_NODE_NUMS]; static struct device *__f4_dev[MAX_NODE_NUMS]; -static unsigned fx_devs = 0; +static unsigned int fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { @@ -122,14 +122,14 @@ static void get_fx_devs(void) printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); } -static u32 f1_read_config32(unsigned reg) +static u32 f1_read_config32(unsigned int reg) { if (fx_devs == 0) get_fx_devs(); return pci_read_config32(__f1_dev[0], reg); } -static void f1_write_config32(unsigned reg, u32 value) +static void f1_write_config32(unsigned int reg, u32 value) { int i; if (fx_devs == 0) @@ -167,11 +167,11 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid, - unsigned goal_link) +static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, + unsigned int goal_link) { struct resource *res; - unsigned nodeid, link = 0; + unsigned int nodeid, link = 0; int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { @@ -196,7 +196,7 @@ static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_node return result; } -static struct resource *amdfam15_find_iopair(struct device *dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link) { struct resource *resource; u32 free_reg, reg; @@ -301,7 +301,7 @@ static void read_resources(struct device *dev) static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; - unsigned reg, link_num; + unsigned int reg, link_num; char buf[50]; /* Make certain the resource has actually been set */ @@ -347,7 +347,7 @@ static void set_resource(struct device *dev, struct resource *resource, u32 node * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(struct device *dev, unsigned nodeid) +static void create_vga_resource(struct device *dev, unsigned int nodeid) { struct bus *link; @@ -377,7 +377,7 @@ static void create_vga_resource(struct device *dev, unsigned nodeid) static void set_resources(struct device *dev) { - unsigned nodeid; + unsigned int nodeid; struct bus *bus; struct resource *res; @@ -658,7 +658,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } @@ -791,8 +791,8 @@ static void cpu_bus_scan(struct device *dev) int i,j; int coreid_bits; int core_max = 0; - unsigned ApicIdCoreIdSize; - unsigned core_nums; + unsigned int ApicIdCoreIdSize; + unsigned int core_nums; int siblings = 0; unsigned int family; u32 modules = 0; @@ -830,7 +830,7 @@ static void cpu_bus_scan(struct device *dev) cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { struct device *cdb_dev; - unsigned devn; + unsigned int devn; struct bus *pbus; devn = DEV_CDB + i; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index ba17c614e5..27e14f5df5 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -882,7 +882,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G mem_hole.node_id = i; break; //only one hole } diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 8a336e6f0a..ba07b3e69b 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -434,7 +434,7 @@ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) * @param dimm_socket_address SMBus address of DIMM socket to interrogate. * @return log2(number of bits) for each side of the DIMM. */ -static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) +static struct dimm_size spd_get_dimm_size(unsigned int dimm_socket_address) { int value; @@ -757,7 +757,7 @@ DIMM-independent configuration functions: * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). * @return New multiple of 64 MB total DRAM in the system. */ -static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index) +static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned int dimm_index) { int i; diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 7a30b761c5..a2c7643fb0 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -175,7 +175,7 @@ void get_gmch_info(sysinfo_t *sysinfo) printk(BIOS_SPEW, "GMCH supports DDR3 with %d MT or less\n", sysinfo->max_ddr3_mt); } - const unsigned max_fsb = (capid >> 28) & 0x3; + const unsigned int max_fsb = (capid >> 28) & 0x3; switch (max_fsb) { case 1: sysinfo->max_fsb_mhz = 1067; diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 3f5dbca8fc..8b1e29287d 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -22,7 +22,7 @@ typedef struct { u32 addr[RANKS_PER_CHANNEL]; - unsigned count; + unsigned int count; } address_bunch_t; /* Read Training. */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index ca446e25a7..2081a396a1 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -205,7 +205,7 @@ static inline void gtt_write_regs(const struct gt_reg *gt) #define GTT_RETRY 1000 int gtt_poll(u32 reg, u32 mask, u32 value) { - unsigned try = GTT_RETRY; + unsigned int try = GTT_RETRY; u32 data; while (try--) { diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c index 9518618825..7df639b6bd 100644 --- a/src/northbridge/intel/i440bx/debug.c +++ b/src/northbridge/intel/i440bx/debug.c @@ -21,7 +21,7 @@ void dump_spd_registers(void) int i; printk(BIOS_DEBUG, "\n"); for (i = 0; i < DIMM_SOCKETS; i++) { - unsigned device; + unsigned int device; device = DIMM0 + i; if (device) { int j; @@ -45,7 +45,7 @@ void dump_spd_registers(void) } } -void dump_pci_device(unsigned dev) +void dump_pci_device(unsigned int dev) { int i; printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7); diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 4711359181..448f8d69be 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -31,7 +31,7 @@ void sdram_initialize(void); /* Debug */ #if CONFIG(DEBUG_RAM_SETUP) void dump_spd_registers(void); -void dump_pci_device(unsigned dev); +void dump_pci_device(unsigned int dev); #else #define dump_spd_registers() #endif diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 903ee273e1..61fc2d2939 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -65,7 +65,7 @@ void gtt_write(u32 reg, u32 data) #define GTT_RETRY 1000 int gtt_poll(u32 reg, u32 mask, u32 value) { - unsigned try = GTT_RETRY; + unsigned int try = GTT_RETRY; u32 data; while (try--) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 6ec76e1443..39270ed72b 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -133,7 +133,7 @@ static void mc_read_resources(struct device *dev) D0F0_TOUUD); printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); - printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned)TOUUD); + printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)TOUUD); /* Report the memory regions */ ram_resource(dev, 3, 0, 640); diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 1fca4c487b..21c13d9035 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -207,13 +207,13 @@ struct raminfo { u8 mode4030[2]; u16 avg4044[2]; u16 max4048[2]; - unsigned total_memory_mb; - unsigned interleaved_part_mb; - unsigned non_interleaved_part_mb; + unsigned int total_memory_mb; + unsigned int interleaved_part_mb; + unsigned int non_interleaved_part_mb; u32 heci_bar; u64 heci_uma_addr; - unsigned memory_reserved_for_heci_mb; + unsigned int memory_reserved_for_heci_mb; struct ram_training training; u32 last_500_command[2]; @@ -549,14 +549,14 @@ enum { static void calculate_timings(struct raminfo *info) { - unsigned cycletime; - unsigned cas_latency_time; - unsigned supported_cas_latencies; - unsigned channel, slot; - unsigned clock_speed_index; - unsigned min_cas_latency; - unsigned cas_latency; - unsigned max_clock_index; + unsigned int cycletime; + unsigned int cas_latency_time; + unsigned int supported_cas_latencies; + unsigned int channel, slot; + unsigned int clock_speed_index; + unsigned int min_cas_latency; + unsigned int cas_latency; + unsigned int max_clock_index; /* Find common CAS latency */ supported_cas_latencies = 0x3fe; @@ -579,7 +579,7 @@ static void calculate_timings(struct raminfo *info) for (channel = 0; channel < NUM_CHANNELS; channel++) for (slot = 0; slot < NUM_SLOTS; slot++) if (info->populated_ranks[channel][slot][0]) { - unsigned timebase; + unsigned int timebase; timebase = 1000 * info-> @@ -627,9 +627,9 @@ static void calculate_timings(struct raminfo *info) static void program_base_timings(struct raminfo *info) { - unsigned channel; - unsigned slot, rank, lane; - unsigned extended_silicon_revision; + unsigned int channel; + unsigned int slot, rank, lane; + unsigned int extended_silicon_revision; int i; extended_silicon_revision = info->silicon_revision; @@ -790,30 +790,30 @@ static unsigned int cycle_ps(struct raminfo *info) } /* Frequency in 1.(1)=10/9 MHz units. */ -static unsigned frequency_11(struct raminfo *info) +static unsigned int frequency_11(struct raminfo *info) { return (info->clock_speed_index + 3) * 120; } /* Frequency in 0.1 MHz units. */ -static unsigned frequency_01(struct raminfo *info) +static unsigned int frequency_01(struct raminfo *info) { return 100 * frequency_11(info) / 9; } -static unsigned ps_to_halfcycles(struct raminfo *info, unsigned int ps) +static unsigned int ps_to_halfcycles(struct raminfo *info, unsigned int ps) { return (frequency_11(info) * 2) * ps / 900000; } -static unsigned ns_to_cycles(struct raminfo *info, unsigned int ns) +static unsigned int ns_to_cycles(struct raminfo *info, unsigned int ns) { return (frequency_11(info)) * ns / 900; } static void compute_derived_timings(struct raminfo *info) { - unsigned channel, slot, rank; + unsigned int channel, slot, rank; int extended_silicon_revision; int some_delay_1_ps; int some_delay_2_ps; @@ -1157,7 +1157,7 @@ static void jedec_init(struct raminfo *info) static void program_modules_memory_map(struct raminfo *info, int pre_jedec) { - unsigned channel, slot, rank; + unsigned int channel, slot, rank; unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */ unsigned int channel_0_non_interleaved; @@ -1196,7 +1196,7 @@ static void program_board_delay(struct raminfo *info) int some_delay_ns; int some_delay_3_half_cycles; - unsigned channel, i; + unsigned int channel, i; int high_multiplier; int lane_3_delay; int cas_latency_derived; @@ -1234,7 +1234,7 @@ static void program_board_delay(struct raminfo *info) MCHBAR16(0x125) = 0x1360; MCHBAR8(0x127) = 0x40; if (info->fsb_frequency < frequency_11(info) / 2) { - unsigned some_delay_2_half_cycles; + unsigned int some_delay_2_half_cycles; high_multiplier = 1; some_delay_2_half_cycles = ps_to_halfcycles(info, ((3 * @@ -1487,7 +1487,7 @@ static void collect_system_info(struct raminfo *info) { u32 capid0[3]; int i; - unsigned channel; + unsigned int channel; /* Wait for some bit, maybe TXT clear. */ while (!(read8((u8 *)0xfed40000) & (1 << 7))) @@ -3204,9 +3204,9 @@ static void ram_training(struct raminfo *info) MCHBAR16(0xfc4) = saved_fc4; } -static unsigned gcd(unsigned a, unsigned b) +static unsigned int gcd(unsigned int a, unsigned int b) { - unsigned t; + unsigned int t; if (a > b) { t = a; a = b; @@ -3226,7 +3226,7 @@ static inline int div_roundup(int a, int b) return DIV_ROUND_UP(a, b); } -static unsigned lcm(unsigned a, unsigned b) +static unsigned int lcm(unsigned int a, unsigned int b) { return (a * b) / gcd(a, b); } @@ -3723,7 +3723,7 @@ void chipset_init(const int s3resume) void raminit(const int s3resume, const u8 *spd_addrmap) { - unsigned channel, slot, lane, rank; + unsigned int channel, slot, lane, rank; int i; struct raminfo info; u8 x2ca8; diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index 0c4f33bc11..eccd743012 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -43,7 +43,7 @@ static inline uint8_t vbnv_data(int index) /* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial. */ static uint8_t crc8_vbnv(const uint8_t *data, int len) { - unsigned crc = 0; + unsigned int crc = 0; int i, j; for (j = len; j; j--, data++) { -- cgit v1.2.3