From 4852dec1ab21e6c6e32eb85354ce4f4182537442 Mon Sep 17 00:00:00 2001 From: david Date: Tue, 29 Dec 2015 15:02:04 +0800 Subject: intel/skylake: Add gpio macro for unused GPIO pins Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and GPIO TX/RX will be disabled. BUG=none BRANCH=none TEST=Build and boot lars Change-Id: I3a6fcd2f3462e8e0d1273aa80b1599b76b160825 Signed-off-by: Patrick Georgi Original-Commit-Id: 889bfd66dbc918e9fb0ba1b95b63fd7a3bf180d9 Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6 Original-Signed-off-by: David Wu Original-Reviewed-on: https://chromium-review.googlesource.com/319964 Original-Commit-Ready: David Wu Original-Tested-by: David Wu Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Rajneesh Bhardwaj Original-Reviewed-by: Pratikkumar V Prajapati Reviewed-on: https://review.coreboot.org/13628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/skylake/include/soc/gpio.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src') diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 7dec874048..f2246e9116 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -108,6 +108,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); _PAD_CFG(pad_, term_, \ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO)) +/* Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and + GPIO TX/RX will be disabled. */ +#define PAD_CFG_NC(pad_) \ + _PAD_CFG(pad_, NONE, \ + _DW0_VALS(DEEP, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, YES)) + /* General purpose output with termination. */ #define PAD_CFG_TERM_GPO(pad_, val_, term_, rst_) \ _PAD_CFG(pad_, term_, \ -- cgit v1.2.3