From 517750745f7fa4c29771c8fc0e03aa1449e44518 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 15 Feb 2021 15:15:22 +0100 Subject: soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0 events in the SMI# handler, as these events have triggered a SCI. Do not ignore any other SMI# types, since they cannot cause a SCI. Note that these bits are reserved on APL and GLK. However, SoC-specific code already accounts for it. Thus, no special handling is needed here. Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/50750 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- .../common/block/include/intelblocks/smihandler.h | 2 -- src/soc/intel/common/block/smm/smihandler.c | 20 ++++++-------------- 2 files changed, 6 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h index 7cea1dd1ab..437c3215cf 100644 --- a/src/soc/intel/common/block/include/intelblocks/smihandler.h +++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h @@ -46,8 +46,6 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void); */ extern const smi_handler_t southbridge_smi[32]; -#define SMI_HANDLER_SCI_EN(__bit) (1 << (__bit)) - /* * This function should be implemented in SOC specific code to handle * the SMI event on SLP_EN. The default functionality is provided in diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 4625d34e4c..a15bc7c8c5 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -435,16 +435,6 @@ void smihandler_southbridge_espi( mainboard_smi_espi_handler(); } -/* SMI handlers that should be serviced in SCI mode too. */ -static uint32_t smihandler_soc_get_sci_mask(void) -{ - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | - SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); - - return sci_mask; -} - void southbridge_smi_handler(void) { int i; @@ -458,12 +448,14 @@ void southbridge_smi_handler(void) smi_sts = pmc_clear_smi_status(); /* - * In SCI mode, execute only those SMI handlers that have - * declared themselves as available for service in that mode - * using smihandler_soc_get_sci_mask. + * When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI + * instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can + * still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0 + * events in the SMI# handler, as these events have triggered a SCI. + * Do not ignore any other SMI# types, since they cannot cause a SCI. */ if (pmc_read_pm1_control() & SCI_EN) - smi_sts &= smihandler_soc_get_sci_mask(); + smi_sts &= ~(1 << PM1_STS_BIT | 1 << GPE0_STS_BIT); if (!smi_sts) return; -- cgit v1.2.3