From 56c8ef9a91b9d78ca5d1c027e21f8c7f5c96bc8b Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 14 Aug 2015 02:50:44 -0500 Subject: southbridge/amd/sr5650: Use correct PCI configuration block offset Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/12049 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Paul Menzel --- src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl index 54259b0e3c..93a74e3507 100644 --- a/src/southbridge/amd/sr5650/acpi/sr5650.asl +++ b/src/southbridge/amd/sr5650/acpi/sr5650.asl @@ -15,8 +15,8 @@ */ Scope(\) { - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ /* PIC IRQ mapping registers, C00h-C01h */ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) -- cgit v1.2.3