From 5a22b14d47955a2cce1d51d883a3c0ee4df39df0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 26 Feb 2013 13:49:56 +0200 Subject: Fix socket LGA775 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Models 6ex and 6fx select UDELAY_LAPIC so cannot select contradicting UDELAY_TSC here. Model 1067x requires speedstep. Change-Id: I69d3ec8085912dfbe5fe31c81fa0a437228fa48f Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/2525 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/socket_LGA775/Kconfig | 1 - src/cpu/intel/socket_LGA775/Makefile.inc | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index dfb3181096..e5c687a5e6 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -14,7 +14,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_1067X select MMX select SSE - select UDELAY_TSC select SIPI_VECTOR_IN_ROM config DCACHE_RAM_SIZE diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 100b4d8e93..ea68ab1a5c 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -13,5 +13,6 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +subdirs-y += ../speedstep cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc -- cgit v1.2.3