From 6b43055b7a51bd3e27578bbb544aa638228f6eaf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 22 Jan 2021 07:52:43 +0200 Subject: ELOG: Add const qualifier for chipset_power_state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is never allowed for ELOG to modify the state. Change-Id: Ie24df3969a3744f27b23997471666e2490e24b84 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/49820 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons --- src/soc/intel/alderlake/elog.c | 4 ++-- src/soc/intel/apollolake/elog.c | 4 ++-- src/soc/intel/broadwell/pch/elog.c | 4 ++-- src/soc/intel/cannonlake/elog.c | 4 ++-- src/soc/intel/elkhartlake/elog.c | 4 ++-- src/soc/intel/icelake/elog.c | 4 ++-- src/soc/intel/jasperlake/elog.c | 4 ++-- src/soc/intel/skylake/elog.c | 4 ++-- src/soc/intel/tigerlake/elog.c | 4 ++-- 9 files changed, 18 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 84f0a7ed4f..8ec1107554 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -20,7 +20,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -54,7 +54,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index b65ab10e6d..d17d407413 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -23,7 +23,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { const struct xhci_wake_info xhci_wake_info[] = { { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, @@ -65,7 +65,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE0_D], ps->gpe0_en[GPE0_D], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* RTC Reset */ if (ps->gen_pmcon1 & RPS) diff --git a/src/soc/intel/broadwell/pch/elog.c b/src/soc/intel/broadwell/pch/elog.c index 9271e27872..1d4d773fcd 100644 --- a/src/soc/intel/broadwell/pch/elog.c +++ b/src/soc/intel/broadwell/pch/elog.c @@ -20,7 +20,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -56,7 +56,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_94_64], ps->gpe0_en[GPE_94_64], 64); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip Status */ if (ps->gen_pmcon2 & THERMTRIP_STS) diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 104a78c2ab..4c39988fff 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -91,7 +91,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -125,7 +125,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/elkhartlake/elog.c b/src/soc/intel/elkhartlake/elog.c index c88efc81bc..14e463c961 100644 --- a/src/soc/intel/elkhartlake/elog.c +++ b/src/soc/intel/elkhartlake/elog.c @@ -20,7 +20,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -54,7 +54,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/icelake/elog.c b/src/soc/intel/icelake/elog.c index 235dc6e3cf..4967fde001 100644 --- a/src/soc/intel/icelake/elog.c +++ b/src/soc/intel/icelake/elog.c @@ -20,7 +20,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -54,7 +54,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index cb9625a675..ccf6fd048b 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -100,7 +100,7 @@ static void pch_log_pme_internal_wake_source(void) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -134,7 +134,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 1332e2d7cd..c9b719fadf 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -131,7 +131,7 @@ static void pch_log_rp_wake_source(void) } } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -173,7 +173,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { bool deep_sx; diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 7f40a37d2f..878959a9b5 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -126,7 +126,7 @@ static void pch_log_pme_internal_wake_source(void) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); } -static void pch_log_wake_source(struct chipset_power_state *ps) +static void pch_log_wake_source(const struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) @@ -160,7 +160,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } -static void pch_log_power_and_resets(struct chipset_power_state *ps) +static void pch_log_power_and_resets(const struct chipset_power_state *ps) { /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) -- cgit v1.2.3