From 6c9737b1ac5b71f705350a960dee0e68b9afb440 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 8 Jul 2018 12:30:02 +0200 Subject: src/{arch,commonlib,cpu}: Use "foo *bar" instead of "foo* bar" Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/26942 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/arch/x86/cpu.c | 2 +- src/commonlib/storage/mmc.c | 2 +- src/commonlib/storage/storage.c | 2 +- src/cpu/amd/car/post_cache_as_ram.c | 2 +- src/cpu/amd/family_10h-family_15h/init_cpus.c | 4 ++-- src/cpu/amd/pi/romstage.c | 4 ++-- src/cpu/intel/turbo/turbo.c | 2 +- src/cpu/via/nano/update_ucode.c | 2 +- 8 files changed, 10 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 7a7c99b0a0..6bbeb59464 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -116,7 +116,7 @@ static struct { { X86_VENDOR_SIS, "SiS SiS SiS ", }, }; -static const char * const x86_vendor_name[] = { +static const char *const x86_vendor_name[] = { [X86_VENDOR_INTEL] = "Intel", [X86_VENDOR_CYRIX] = "Cyrix", [X86_VENDOR_AMD] = "AMD", diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index d88e469291..e09d826782 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -529,7 +529,7 @@ int mmc_set_partition(struct storage_media *media, const char *mmc_partition_name(struct storage_media *media, unsigned int partition_number) { - static const char * const partition_name[8] = { + static const char *const partition_name[8] = { "User", /* 0 */ "Boot 1", /* 1 */ "Boot 2", /* 2 */ diff --git a/src/commonlib/storage/storage.c b/src/commonlib/storage/storage.c index d2b566f71e..927e12ff30 100644 --- a/src/commonlib/storage/storage.c +++ b/src/commonlib/storage/storage.c @@ -31,7 +31,7 @@ #define HEX_CAPACITY_MULTIPLIER 1024ULL struct capacity { - const char * const units; + const char *const units; uint64_t bytes; }; diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 2fb46d286a..a96811365a 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -121,7 +121,7 @@ static void vErrata343(void) wrmsr(BU_CFG2_MSR, msr); } -asmlinkage void * post_cache_as_ram(void) +asmlinkage void *post_cache_as_ram(void) { uint32_t family = amd_fam1x_cpu_family(); int s3resume = 0; diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 0ecd040253..f1a607b6ea 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -377,7 +377,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH; uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE; uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size; - void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); + void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); if (((void*)(sysinfo + 1)) > lower_stack_region_boundary) printk(BIOS_WARNING, "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n", @@ -825,7 +825,7 @@ static void AMD_SetupPSIVID_d(u32 platform_type, u8 node) * * Returns the offset of the link register. */ -static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset) +static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset) { u32 reg; u32 val; diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c index 9a5fbac003..aa14826149 100644 --- a/src/cpu/amd/pi/romstage.c +++ b/src/cpu/amd/pi/romstage.c @@ -28,7 +28,7 @@ void asmlinkage early_all_cores(void) amd_initmmio(); } -void * asmlinkage romstage_main(unsigned long bist) +void *asmlinkage romstage_main(unsigned long bist) { int s3resume = 0; u8 initial_apic_id = cpuid_ebx(1) >> 24; @@ -45,7 +45,7 @@ void * asmlinkage romstage_main(unsigned long bist) stack_top += HIGH_ROMSTAGE_STACK_SIZE; printk(BIOS_DEBUG, "Move CAR stack.\n"); - return (void*)stack_top; + return (void *)stack_top; } void asmlinkage romstage_after_car(void) diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index 9b9387098c..5583c46ea9 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -42,7 +42,7 @@ static inline void set_global_turbo_state(int state) } #endif -static const char * const turbo_state_desc[] = { +static const char *const turbo_state_desc[] = { [TURBO_UNKNOWN] = "unknown", [TURBO_UNAVAILABLE] = "unavailable", [TURBO_DISABLED] = "available but hidden", diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 9ff66e7db8..7c631a6dda 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -61,7 +61,7 @@ static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) * Two's complement done over the entire file, including the header */ int i; u32 check = 0; - u32 *raw = (void*) ucode; + u32 *raw = (void *) ucode; for (i = 0; i < ((ucode->total_size) >> 2); i++) { check += raw[i]; } -- cgit v1.2.3