From 6fcb9b00c8b7f820bb5ef81a83a24cd656654272 Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Wed, 18 Apr 2018 08:06:33 -0700 Subject: soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structure The GPIO definition structure has evolved to a point where it's no longer specific to stoneyridge, though probably still specific to AMD. Therefore, rename the GPIO declaration structure removing stoneyridge from it. BUG=b:72875858 TEST=Build kahlee, grunt, gardenia. Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543 Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/25726 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/mainboard/amd/gardenia/bootblock/bootblock.c | 2 +- src/mainboard/amd/gardenia/gpio.c | 8 ++++---- src/mainboard/amd/gardenia/gpio.h | 4 ++-- src/mainboard/amd/gardenia/mainboard.c | 2 +- src/mainboard/google/kahlee/bootblock/bootblock.c | 2 +- src/mainboard/google/kahlee/mainboard.c | 2 +- src/mainboard/google/kahlee/variants/baseboard/gpio.c | 12 ++++++------ .../kahlee/variants/baseboard/include/baseboard/variants.h | 4 ++-- src/mainboard/google/kahlee/variants/kahlee/gpio.c | 8 ++++---- src/soc/amd/stoneyridge/include/soc/southbridge.h | 5 ++--- src/soc/amd/stoneyridge/southbridge.c | 3 +-- 11 files changed, 25 insertions(+), 27 deletions(-) (limited to 'src') diff --git a/src/mainboard/amd/gardenia/bootblock/bootblock.c b/src/mainboard/amd/gardenia/bootblock/bootblock.c index cb2a13516b..140bc07529 100644 --- a/src/mainboard/amd/gardenia/bootblock/bootblock.c +++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c @@ -21,7 +21,7 @@ void bootblock_mainboard_early_init(void) { size_t num_gpios; - const struct soc_amd_stoneyridge_gpio *gpios; + const struct soc_amd_gpio *gpios; gpios = early_gpio_table(&num_gpios); sb_program_gpios(gpios, num_gpios); } diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c index 6672ea5c21..7c5f47b25a 100644 --- a/src/mainboard/amd/gardenia/gpio.c +++ b/src/mainboard/amd/gardenia/gpio.c @@ -24,7 +24,7 @@ * bootblock while GPIO pins used only by the OS should be initialized at * ramstage. */ -const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { +static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* NFC PU */ PAD_GPO(GPIO_64, HIGH), /* PCIe presence detect */ @@ -45,7 +45,7 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), }; -const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { +static const struct soc_amd_gpio gpio_set_stage_ram[] = { /* BT radio disable */ PAD_GPO(GPIO_14, HIGH), /* NFC wake */ @@ -56,13 +56,13 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { PAD_GPO(GPIO_70, HIGH), }; -const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size) +const struct soc_amd_gpio *early_gpio_table(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage_reset); return gpio_set_stage_reset; } -const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size) +const struct soc_amd_gpio *gpio_table(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage_ram); return gpio_set_stage_ram; diff --git a/src/mainboard/amd/gardenia/gpio.h b/src/mainboard/amd/gardenia/gpio.h index f3869448f5..1d3a8a2508 100644 --- a/src/mainboard/amd/gardenia/gpio.h +++ b/src/mainboard/amd/gardenia/gpio.h @@ -16,7 +16,7 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H -const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size); -const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size); +const struct soc_amd_gpio *early_gpio_table(size_t *size); +const struct soc_amd_gpio *gpio_table(size_t *size); #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 71fa257318..9853803896 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -81,7 +81,7 @@ static void pirq_setup(void) static void mainboard_init(void *chip_info) { size_t num_gpios; - const struct soc_amd_stoneyridge_gpio *gpios; + const struct soc_amd_gpio *gpios; gpios = gpio_table(&num_gpios); sb_program_gpios(gpios, num_gpios); } diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 641287c1bd..843bf4ece5 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -23,7 +23,7 @@ void bootblock_mainboard_early_init(void) { size_t num_gpios; - const struct soc_amd_stoneyridge_gpio *gpios; + const struct soc_amd_gpio *gpios; /* Enable the EC as soon as we have visibility */ mainboard_ec_init(); diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index e82569e485..cd37c90f28 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -159,7 +159,7 @@ static void mainboard_init(void *chip_info) size_t num; int boardid = board_id(); size_t num_gpios; - const struct soc_amd_stoneyridge_gpio *gpios; + const struct soc_amd_gpio *gpios; printk(BIOS_INFO, "Board ID: %d\n", boardid); diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 6b81b3ef91..8f4ba5c26f 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -25,7 +25,7 @@ * bootblock while GPIO pins used only by the OS should be initialized at * ramstage. */ -const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset_old[] = { +static const struct soc_amd_gpio gpio_set_stage_reset_old[] = { /* GPIO_0 - EC_PCH_PWR_BTN_ODL */ PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), @@ -196,7 +196,7 @@ const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset_old[] = { PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), }; -const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { +static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* GPIO_0 - EC_PCH_PWR_BTN_ODL */ PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), @@ -370,7 +370,7 @@ const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), }; -const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram_old[] = { +static const struct soc_amd_gpio gpio_set_stage_ram_old[] = { /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ PAD_NF(GPIO_2, WAKE_L, PULL_UP), @@ -429,7 +429,7 @@ const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram_old[] = { PAD_GPI(GPIO_135, PULL_UP), }; -const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { +static const struct soc_amd_gpio gpio_set_stage_ram[] = { /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ PAD_NF(GPIO_2, WAKE_L, PULL_UP), @@ -486,7 +486,7 @@ const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { }; const __attribute__((weak)) -struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size) +struct soc_amd_gpio *variant_early_gpio_table(size_t *size) { if (board_id() < 2) { *size = ARRAY_SIZE(gpio_set_stage_reset_old); @@ -498,7 +498,7 @@ struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size) } const __attribute__((weak)) -struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size) +struct soc_amd_gpio *variant_gpio_table(size_t *size) { if (board_id() < 2) { *size = ARRAY_SIZE(gpio_set_stage_ram_old); diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index e827a72d3e..fc754b5533 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -28,8 +28,8 @@ uint8_t variant_board_sku(void); int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len); int variant_get_xhci_oc_map(uint16_t *usb_oc_map); int variant_get_ehci_oc_map(uint16_t *usb_oc_map); -const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size); -const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_gpio_table(size_t *size); void variant_romstage_entry(int s3_resume); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c index 29d7817678..8f30e4b40e 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c +++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c @@ -24,7 +24,7 @@ * bootblock while GPIO pins used only by the OS should be initialized at * ramstage. */ -const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { +static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* AGPIO2, to become event generator */ PAD_GPI(GPIO_2, PULL_UP), @@ -71,7 +71,7 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { PAD_GPI(GPIO_144, PULL_NONE), }; -const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { +static const struct soc_amd_gpio gpio_set_stage_ram[] = { /* AGPIO 12 */ PAD_GPI(GPIO_12, PULL_UP), @@ -102,13 +102,13 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { PAD_GPO(GPIO_119, HIGH), }; -const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size) +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage_reset); return gpio_set_stage_reset; } -const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size) +const struct soc_amd_gpio *variant_gpio_table(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage_ram); return gpio_set_stage_ram; diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index c0a48b301e..eed7457f20 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -352,7 +352,7 @@ #define FCH_AOAC_STAT0 BIT(6) #define FCH_AOAC_STAT1 BIT(7) -struct soc_amd_stoneyridge_gpio { +struct soc_amd_gpio { uint8_t gpio; uint8_t function; uint8_t control; @@ -449,8 +449,7 @@ uint64_t get_uma_base(void); * * @return none */ -void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr, - size_t size); +void sb_program_gpios(const struct soc_amd_gpio *gpio_ptr, size_t size); /** * @brief Find the size of a particular wide IO * diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index a2a54c211c..7465b64584 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -172,8 +172,7 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) return irq_association; } -void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr, - size_t size) +void sb_program_gpios(const struct soc_amd_gpio *gpio_ptr, size_t size) { void *tmp_ptr; uint8_t control, mux, index; -- cgit v1.2.3