From 7c2ae7ae53ac2bc4dadc55ba5445d0556ee32251 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 24 Jun 2013 03:14:41 -0700 Subject: exynos5420: Clock the mmc blocks off of the mpll. The exynos manual suggests hooking the mmc ip blocks to the mpll. They had been set to use a different pll. This changes them over and modifies the divider so that the frequency stays the same. Change-Id: I85103388d6cc2c63d1ca004654fc08fcc8929962 Signed-off-by: Gabe Black Reviewed-on: http://review.coreboot.org/3703 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/samsung/exynos5420/setup.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index 7d63772832..e89ed8eee4 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -222,7 +222,7 @@ struct exynos5_phy_control; #define CLK_DIV_CPU0_VAL 0x01440020 /* CLK_SRC_TOP */ -#define CLK_SRC_TOP0_VAL 0x12221222 +#define CLK_SRC_TOP0_VAL 0x12222222 #define CLK_SRC_TOP1_VAL 0x00100200 #define CLK_SRC_TOP2_VAL 0x11101000 #define CLK_SRC_TOP3_VAL 0x11111111 @@ -231,7 +231,7 @@ struct exynos5_phy_control; #define CLK_SRC_TOP7_VAL 0x00022200 /* CLK_DIV_TOP */ -#define CLK_DIV_TOP0_VAL 0x23712311 +#define CLK_DIV_TOP0_VAL 0x23713311 #define CLK_DIV_TOP1_VAL 0x13100B00 #define CLK_DIV_TOP2_VAL 0x11101100 -- cgit v1.2.3