From 8340666cb18322cbf39110b82d83bf02bfa8c856 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 6 Mar 2014 16:32:18 +0200 Subject: intel/jarrell: Apply ROMCC workaround MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Taken from intel/xe7501devkit, maybe it had same symptoms once. The call to ich5_watchdog_on() has side-effect of exploding the requirements for ROMCC internal arrays at compile-time. The hard-coded limit in question is MAX_RHS in util/romcc.c, the default of 127 comes from the rhs field defined with 7 bits. Before this patch intel/jarrell builds were using upto MAX_RHS=102, while other ROMCC boards built even with MAX_RHS=10. This workaround brings intel/jarrell to the same level. Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/5348 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/mainboard/intel/jarrell/romstage.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index c6f014c08b..bddb34afe6 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -102,4 +102,8 @@ static void main(unsigned long bist) dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif + /* NOTE: ROMCC dies with an internal compiler error if the + * following line is removed. + */ + print_debug("SDRAM is up.\n"); } -- cgit v1.2.3