From 8e23bac97ec66a49f9ddb1a4069e4e68666833fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 17 Aug 2019 06:47:50 +0300 Subject: intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove cases of __PRE_RAM__ and other preprocessor guards. Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928 Reviewed-by: Furquan Shaikh Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_0/fastboot_cache.c | 6 ----- src/drivers/intel/fsp1_0/fsp_util.c | 26 ++++++---------------- src/drivers/intel/fsp1_0/fsp_util.h | 10 --------- .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 14 +++--------- src/soc/intel/baytrail/include/soc/msr.h | 1 + src/soc/intel/baytrail/include/soc/ramstage.h | 1 - src/soc/intel/baytrail/include/soc/romstage.h | 6 ----- src/soc/intel/baytrail/romstage/romstage.c | 4 +++- src/soc/intel/baytrail/tsc_freq.c | 9 -------- src/soc/intel/fsp_baytrail/cpu.c | 1 + src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 13 ++--------- src/soc/intel/fsp_baytrail/gpio.c | 5 ----- src/soc/intel/fsp_baytrail/include/soc/baytrail.h | 14 ++++++------ src/soc/intel/fsp_baytrail/include/soc/pmc.h | 2 ++ src/soc/intel/fsp_baytrail/include/soc/ramstage.h | 1 - src/soc/intel/fsp_baytrail/include/soc/romstage.h | 13 ----------- .../intel/fsp_baytrail/romstage/report_platform.c | 2 +- src/soc/intel/fsp_baytrail/romstage/romstage.c | 3 ++- src/soc/intel/fsp_baytrail/tsc_freq.c | 10 +-------- src/southbridge/intel/fsp_rangeley/acpi.c | 1 + src/southbridge/intel/fsp_rangeley/lpc.c | 1 + src/southbridge/intel/fsp_rangeley/romstage.h | 4 ---- src/southbridge/intel/fsp_rangeley/sata.c | 1 + src/southbridge/intel/fsp_rangeley/soc.h | 19 +++++++--------- src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c | 6 ----- 25 files changed, 41 insertions(+), 132 deletions(-) (limited to 'src') diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c index 34761a05be..7eba875e51 100644 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ b/src/drivers/intel/fsp1_0/fastboot_cache.c @@ -116,10 +116,6 @@ static struct mrc_data_container *find_current_mrc_cache_local return mrc_cache; } -/* SPI code needs malloc/free. - * Also unknown if writing flash from XIP-flash code is a good idea - */ -#if !defined(__PRE_RAM__) /* find the first empty block in the MRC cache area. * If there's none, return NULL. * @@ -221,8 +217,6 @@ void update_mrc_cache(void *unused) current->mrc_data_size + sizeof(*current), current); } -#endif /* !defined(__PRE_RAM__) */ - void *find_and_set_fastboot_cache(void) { struct mrc_data_container *mrc_cache = NULL; diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index d787c7beca..a7f3017230 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -25,7 +25,6 @@ #include #include -#ifndef __PRE_RAM__ /* Globals pointers for FSP structures */ void *FspHobListPtr = NULL; FSP_INFO_HEADER *fsp_header_ptr = NULL; @@ -60,9 +59,6 @@ void FspNotify (u32 Phase) if (Status != 0) printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status); } -#endif /* #ifndef __PRE_RAM__ */ - -#ifdef __PRE_RAM__ /* The FSP returns here after the fsp_early_init call */ static void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) @@ -115,12 +111,10 @@ void __noreturn fsp_early_init (FSP_INFO_HEADER *fsp_ptr) /* Should never return. Control will continue from ContinuationFunc */ die("Uh Oh! FspInitApi returned"); } -#endif /* __PRE_RAM__ */ volatile u8 *find_fsp() { - -#ifdef __PRE_RAM__ +#if ENV_ROMSTAGE volatile register u8 *fsp_ptr asm ("eax"); /* Entry point for CAR assembly routine */ @@ -130,7 +124,7 @@ volatile u8 *find_fsp() ); #else volatile u8 *fsp_ptr; -#endif /* __PRE_RAM__ */ +#endif /* The FSP is stored in CBFS */ fsp_ptr = (u8 *) CONFIG_FSP_LOC; @@ -225,8 +219,6 @@ void *find_fsp_reserved_mem(void *hob_list_ptr) } #endif /* FSP_RESERVE_MEMORY_SIZE */ -#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ - void print_fsp_info(void) { if (fsp_header_ptr == NULL) @@ -249,12 +241,10 @@ void print_fsp_info(void) { (u8)(fsp_header_ptr->ImageRevision & 0xff)); } - -#if CONFIG(ENABLE_MRC_CACHE) /** * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM */ -int save_mrc_data(void *hob_start) +static int save_mrc_data(void *hob_start) { u32 *mrc_hob; u32 *mrc_hob_data; @@ -307,7 +297,6 @@ int save_mrc_data(void *hob_start) hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len / 4); return (1); } -#endif /* CONFIG_ENABLE_MRC_CACHE */ static void find_fsp_hob_update_mrc(void *unused) { @@ -319,13 +308,13 @@ static void find_fsp_hob_update_mrc(void *unused) } else { /* 0x0000: Print all types */ print_hob_type_structure(0x000, FspHobListPtr); + } - #if CONFIG(ENABLE_MRC_CACHE) + if (CONFIG(ENABLE_MRC_CACHE)) { if (save_mrc_data(FspHobListPtr)) update_mrc_cache(NULL); else printk(BIOS_DEBUG,"Not updating MRC data in flash.\n"); - #endif } } @@ -356,11 +345,10 @@ static void fsp_finalize(void *unused) printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); } + /* Set up for the ramstage FSP calls */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL); /* Update the MRC/fast boot cache as part of the late table writing stage */ -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - find_fsp_hob_update_mrc, NULL); -#endif /* #ifndef __PRE_RAM__ */ +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL); diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index e09bbd9b65..a368c7f089 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -21,10 +21,7 @@ #include "fsp_values.h" -#if CONFIG(ENABLE_MRC_CACHE) -int save_mrc_data(void *hob_start); void *find_and_set_fastboot_cache(void); -#endif volatile u8 *find_fsp(void); void fsp_early_init(FSP_INFO_HEADER *fsp_info); @@ -65,7 +62,6 @@ void printguid(EFI_GUID *guid); #define EFI_HOB_TYPE_HANDOFF 0x0001 #define EFI_HOB_TYPE_MEMORY_POOL 0x0007 -#if CONFIG(ENABLE_MRC_CACHE) #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) @@ -79,11 +75,7 @@ struct mrc_data_container { struct mrc_data_container *find_current_mrc_cache(void); -#if !defined(__PRE_RAM__) void update_mrc_cache(void *unused); -#endif - -#endif /* The offset in bytes from the start of the info structure */ #define FSP_IMAGE_SIG_LOC 0 @@ -99,9 +91,7 @@ void update_mrc_cache(void *unused); #define ERROR_INFO_HEAD_SIG_MISMATCH 5 #define ERROR_FSP_SIG_MISMATCH 6 -#ifndef __PRE_RAM__ extern void *FspHobListPtr; -#endif #define UPD_DEFAULT_CHECK(member) \ if (config->member != UPD_DEFAULT) { \ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 04a696c2c2..43e71f4d3d 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -26,12 +26,6 @@ #include #include "../chip.h" -#ifdef __PRE_RAM__ -#include -#endif - -#ifdef __PRE_RAM__ - /* Copy the default UPD region and settings to a buffer for modification */ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) @@ -96,9 +90,9 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) if (config->MrcRmtCpgcNumBursts) { UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts; } -#if CONFIG(ENABLE_FSP_FAST_BOOT) - UpdData->PcdFastboot = UPD_ENABLE; -#endif + if (CONFIG(ENABLE_FSP_FAST_BOOT)) + UpdData->PcdFastboot = UPD_ENABLE; + /* * Loop through all the SOC devices in the devicetree * enabling and disabling them as requested. @@ -164,5 +158,3 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, return; } - -#endif /* __PRE_RAM__ */ diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index e39758c64b..5038bf87db 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -40,5 +40,6 @@ /* Read BCLK from MSR */ unsigned bus_freq_khz(void); +void set_max_freq(void); #endif /* _BAYTRAIL_MSR_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h index d20859d055..f98a79b2ea 100644 --- a/src/soc/intel/baytrail/include/soc/ramstage.h +++ b/src/soc/intel/baytrail/include/soc/ramstage.h @@ -23,7 +23,6 @@ * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); void baytrail_init_cpus(struct device *dev); -void set_max_freq(void); void southcluster_enable_dev(struct device *dev); #if CONFIG(HAVE_REFCODE_BLOB) void baytrail_run_reference_code(void); diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 3dc24f0777..8ea2d699c7 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -35,12 +35,6 @@ void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); void punit_init(void); -void set_max_freq(void); - -#if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif #endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index cf6a856b7b..7a413d9c1d 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -131,7 +132,8 @@ static void romstage_main(uint64_t tsc) tco_disable(); - byt_config_com1_and_enable(); + if (CONFIG(ENABLE_BUILTIN_COM1)) + byt_config_com1_and_enable(); console_init(); diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index f9c3014273..5b2d13599d 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -47,13 +47,6 @@ unsigned long tsc_freq_mhz(void) return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; } -#if !defined(__SMM__) -#if !defined(__PRE_RAM__) -#include -#else -#include -#endif - void set_max_freq(void) { msr_t perf_ctl; @@ -76,5 +69,3 @@ void set_max_freq(void) wrmsr(IA32_PERF_CTL, perf_ctl); } - -#endif /* __SMM__ */ diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 7fe8f70581..0c86ce394a 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index f11b206ed4..48f0cdd755 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -31,12 +31,6 @@ #include #include -#ifdef __PRE_RAM__ -#include -#endif - -#ifdef __PRE_RAM__ - /* Copy the default UPD region and settings to a buffer for modification */ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) { @@ -307,10 +301,9 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; -#if CONFIG(ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ - pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); -#endif + if (CONFIG(ENABLE_MRC_CACHE)) + pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); if (prev_sleep_state == ACPI_S3) { /* S3 resume */ @@ -335,5 +328,3 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, return; } - -#endif /* __PRE_RAM__ */ diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 6da1258bf3..3e2499accd 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -29,13 +29,11 @@ * PCU iLB GPIO CFIO_SCORE Address Map * PCU iLB GPIO CFIO_SSUS Address Map */ -#ifndef __PRE_RAM__ static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ 2, 5, 9 }; /* [24:26] */ -#endif static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ @@ -61,8 +59,6 @@ static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = 52, 53, 59, 40 }; /* [40:43] */ -#ifndef __PRE_RAM__ - /* GPIO bank descriptions */ static const struct gpio_bank gpncore_bank = { .gpio_count = GPNCORE_COUNT, @@ -253,7 +249,6 @@ struct soc_gpio_config* __weak mainboard_get_gpios(void) printk(BIOS_DEBUG, "Default/empty GPIO config\n"); return NULL; } -#endif /* #ifndef __PRE_RAM__ */ /** \brief returns the input / output value from an SCORE GPIO * diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 34831b13bb..3a2fcaa635 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -35,23 +35,24 @@ #else #define DEFAULT_RCBA 0xfed1c000 #endif -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__ /* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define SKPAD 0xFC /* SOC types */ #define SOC_TYPE_BAYTRAIL 0x0F1C +/* Everything below this line is ignored in the DSDT */ +#ifndef __ACPI__ #ifndef __ASSEMBLER__ -static inline void barrier(void) { asm("" ::: "memory"); } +#include -#define SKPAD 0xFC +static inline void barrier(void) { asm("" ::: "memory"); } int bridge_silicon_revision(void); void rangeley_early_initialization(void); +void set_max_freq(void); -#ifndef __PRE_RAM__ /* soc.c */ int soc_silicon_revision(void); int soc_silicon_type(void); @@ -60,8 +61,7 @@ void soc_enable(struct device *dev); void report_platform_info(void); -#endif /* __PRE_RAM__ */ #endif /* __ASSEMBLER__ */ - #endif /* __ACPI__ */ + #endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index 75daba540e..71c8e10446 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -283,6 +283,8 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); +uint32_t chipset_prev_sleep_state(uint32_t clear); + #if CONFIG(ELOG) void southcluster_log_state(void); #else diff --git a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h index e8f81bb5c0..45fda9e937 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h @@ -22,7 +22,6 @@ * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); void baytrail_init_cpus(struct device *dev); -void set_max_freq(void); void southcluster_enable_dev(struct device *dev); void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h index 5f0bd8d9c3..dce953993a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h @@ -17,31 +17,18 @@ #ifndef _BAYTRAIL_ROMSTAGE_H_ #define _BAYTRAIL_ROMSTAGE_H_ -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - -void report_platform_info(void); - #include #include void main(FSP_INFO_HEADER *fsp_info_header); -uint32_t chipset_prev_sleep_state(uint32_t clear); #define NUM_ROMSTAGE_TS 4 void tco_disable(void); void punit_init(void); -void set_max_freq(void); void early_mainboard_romstage_entry(void); void late_mainboard_romstage_entry(void); void get_func_disables(uint32_t *mask, uint32_t *mask2); - -#if CONFIG(ENABLE_BUILTIN_COM1) void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif #endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c index 98f35f06d4..2b5dad7ab7 100644 --- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c +++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 35b531a465..f347591599 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -167,7 +167,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) tco_disable(); post_code(0x42); - byt_config_com1_and_enable(); + if (CONFIG(ENABLE_BUILTIN_COM1)) + byt_config_com1_and_enable(); post_code(0x43); console_init(); diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c index f9c3014273..6605575691 100644 --- a/src/soc/intel/fsp_baytrail/tsc_freq.c +++ b/src/soc/intel/fsp_baytrail/tsc_freq.c @@ -17,6 +17,7 @@ #include #include #include +#include unsigned bus_freq_khz(void) { @@ -47,13 +48,6 @@ unsigned long tsc_freq_mhz(void) return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; } -#if !defined(__SMM__) -#if !defined(__PRE_RAM__) -#include -#else -#include -#endif - void set_max_freq(void) { msr_t perf_ctl; @@ -76,5 +70,3 @@ void set_max_freq(void) wrmsr(IA32_PERF_CTL, perf_ctl); } - -#endif /* __SMM__ */ diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index aeb2d9b3bb..5605d41bc7 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -22,6 +22,7 @@ #include #include #include +#include "chip.h" /** diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index d7ae8f6a11..5693bb7e99 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -33,6 +33,7 @@ #include #include #include +#include "chip.h" #include "soc.h" #include "irq.h" #include "nvs.h" diff --git a/src/southbridge/intel/fsp_rangeley/romstage.h b/src/southbridge/intel/fsp_rangeley/romstage.h index 5827b0fe9b..7921d8041b 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.h +++ b/src/southbridge/intel/fsp_rangeley/romstage.h @@ -17,10 +17,6 @@ #ifndef _RANGELEY_ROMSTAGE_H_ #define _RANGELEY_ROMSTAGE_H_ -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - #include #include diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index 58388a2fab..604c56636a 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -21,6 +21,7 @@ #include #include #include +#include "chip.h" #include "soc.h" typedef struct southbridge_intel_fsp_rangeley_config config_t; diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index aceb425ab7..ce5e056514 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -47,29 +47,26 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if defined(__SMM__) && !defined(__ASSEMBLER__) void intel_soc_finalize_smm(void); + +#if !defined(__ROMCC__) +#include +void soc_enable(struct device *dev); +void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt); #endif -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include "chip.h" int soc_silicon_revision(void); int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); -void soc_enable(struct device *dev); -void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); -#if CONFIG(ELOG) void soc_log_state(void); -#endif -#else void enable_smbus(void); void enable_usb_bar(void); -int smbus_read_byte(unsigned device, unsigned address); void rangeley_sb_early_initialization(void); -#endif + +#if ENV_ROMSTAGE +int smbus_read_byte(unsigned int device, unsigned int address); #endif #define MAINBOARD_POWER_OFF 0 diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c index ba56543975..bbcf753dce 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c +++ b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c @@ -43,9 +43,7 @@ are permitted provided that the following conditions are met: // // Pointer to the HOB should be initialized with the output of FSP INIT PARAMS // -#ifndef __PRE_RAM__ extern volatile void *FspHobListPtr; -#endif /** Reads a 64-bit value from memory that may be unaligned. @@ -116,12 +114,8 @@ GetHobList ( VOID ) { -#ifndef __PRE_RAM__ ASSERT (FspHobListPtr != NULL); return ((VOID *)FspHobListPtr); -#else - return ((VOID *)NULL); -#endif } /** -- cgit v1.2.3