From 949491979ccec4242fb4398fa954c0678c72cda2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Sat, 4 Mar 2017 07:51:00 +0200
Subject: amd/union_station: Switch away from AGESA_LEGACY
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change-Id: I706de64ae5d940df70701c8b9dd717f8e212cd0e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
---
 src/mainboard/amd/union_station/Kconfig        |  1 -
 src/mainboard/amd/union_station/OemCustomize.c | 14 +++---
 src/mainboard/amd/union_station/romstage.c     | 65 +-------------------------
 3 files changed, 9 insertions(+), 71 deletions(-)

(limited to 'src')

diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig
index d8b5a34d82..83660bb77c 100644
--- a/src/mainboard/amd/union_station/Kconfig
+++ b/src/mainboard/amd/union_station/Kconfig
@@ -17,7 +17,6 @@ if BOARD_AMD_UNIONSTATION
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select AGESA_LEGACY
 	select CPU_AMD_AGESA_FAMILY14
 	select NORTHBRIDGE_AMD_AGESA_FAMILY14
 	select SOUTHBRIDGE_AMD_CIMX_SB800
diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c
index 6f4dbfc368..00db12c88e 100644
--- a/src/mainboard/amd/union_station/OemCustomize.c
+++ b/src/mainboard/amd/union_station/OemCustomize.c
@@ -22,7 +22,7 @@
 #include "Filecode.h"
 
 #include <string.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/state_machine.h>
 
 #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
 
@@ -42,7 +42,7 @@
  **/
 /*---------------------------------------------------------------------------------------*/
 
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
   AGESA_STATUS         Status;
   VOID                 *BrazosPcieComplexListPtr;
@@ -140,7 +140,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
 
   InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
   InitEarly->GnbConfig.PsppPolicy      = 0;
-	return AGESA_SUCCESS;
 }
 
 /*----------------------------------------------------------------------------------------
@@ -154,12 +153,13 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
  *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
  *  use its default conservative settings.
  */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
   NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
   NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
   PSO_END
 };
 
-const struct OEM_HOOK OemCustomize = {
-	.InitEarly = OemInitEarly,
-};
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 5cd0a8c214..f2b00bc24d 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -13,69 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#include <lib.h>
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
-#include <sb_cimx.h>
-#include "SBPLATFORM.h"
+#include <northbridge/amd/agesa/state_machine.h>
 
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
 {
-	u32 val;
-
-	/* Must come first to enable PCI MMCONF. */
-	amd_initmmio();
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x30);
-		sb_Poweron_Init();
-
-		post_code(0x31);
-		console_init();
-	}
-
-	/* Halt if there was a built in self test failure */
-	post_code(0x34);
-	report_bist_failure(bist);
-
-	/* Load MPB */
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	post_code(0x37);
-	agesawrapper_amdinitreset();
-
-	post_code(0x39);
-	agesawrapper_amdinitearly();
-
-	post_code(0x40);
-	agesawrapper_amdinitpost();
-
-	post_code(0x41);
-	agesawrapper_amdinitenv();
-	amd_initenv();
-
-	post_code(0x50);
-	copy_and_run();
-	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
-
-	post_code(0x54);  /* Should never see this post code. */
 }
-- 
cgit v1.2.3