From 9b0c690c09137d85d9c9280ce082094089ee9032 Mon Sep 17 00:00:00 2001 From: Scott Duplichan Date: Tue, 14 Sep 2010 17:28:41 +0000 Subject: This patch corrects a coding error in the original implementation of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code sets msr c001_102a bit 3 when bit 35 was intended. Signed-off-by: Scott Duplichan Acked-by: Marc Jones git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/car/cache_as_ram.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 218a538c35..e4f1ba426d 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -129,8 +129,8 @@ CAR_FAM10_out: /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */ rdmsr - /* Set bit 35 to 1 in EAX */ - bts $35, %eax + /* Set bit 35 to 1 in EAX:EDX */ + bts $35-32, %edx /* write back the modified register EDX:EAX to the MSR specified in ECX */ wrmsr -- cgit v1.2.3