From 9ff2af2b479e699a77cdb5de3835be25129c37ef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 13 Apr 2020 20:37:36 +0200 Subject: sb/intel/bd82x6x/lpc.c: configure CLKRUN_EN according to SKU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CLKRUN_EN bit available for mobile is reserved on desktop SKUs. PSEUDO_CLKRUN_EN bit available for desktop is reserved for mobile SKUs. Configure these bits accordign to SKU. Signed-off-by: Michał Żygowski Change-Id: I5295eb2bec27c77f800cc2ade9093e97ede47789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40347 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/southbridge/intel/bd82x6x/lpc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 27f45e359b..278e90ac00 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -20,6 +20,7 @@ #include "chip.h" #include "pch.h" #include "nvs.h" +#include #include #include #include @@ -373,7 +374,12 @@ static void enable_clock_gating(struct device *dev) RCBA32_AND_OR(DMIC, ~0UL, 0xf); reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 |= (1 << 2) | (1 << 11); + reg16 &= ~(3 << 2); /* Clear CLKRUN bits for mobile and desktop */ + if (get_platform_type() == PLATFORM_MOBILE) + reg16 |= (1 << 2); /* CLKRUN_EN for mobile */ + else if (get_platform_type() == PLATFORM_DESKTOP_SERVER) + reg16 |= (1 << 3); /* PSEUDO_CLKRUN_EN for desktop */ + reg16 |= (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16); pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); -- cgit v1.2.3