From a1928cfa28e4a589a9f8c1b349edd234c38d87ec Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 13 Nov 2019 10:51:59 +0100 Subject: sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x The northbridge code to set up DMI is not correct and the CIR bits relate to that. This fixes a regression caused by 2437fe9 'sb/intel/i82801gx: Move CIR init to a common place', where payloads hang on southbridge IO. Change-Id: Iabb54d9954d442a1a7b48a6c6e76faa8079a4c71 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36809 Reviewed-by: Angel Pons Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801gx/early_init.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 0bd6198e2c..f91a5dc1d0 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -112,6 +112,9 @@ void i82801gx_early_init(void) RCBA8(OIC) = 0x03; RCBA8(OIC); - ich7_setup_cir(); + /* A lot of CIR bits relate DMI setup which is likely not correctly + done for x4x. The issue is also present on ICH10. */ + if (!CONFIG(NORTHBRIDGE_INTEL_X4X)) + ich7_setup_cir(); } #endif -- cgit v1.2.3