From a8a9f34e9b7be8781c06c9d6fcc39f52bf31bd23 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 24 Dec 2017 08:11:13 +0100 Subject: sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables Both southbridges need to be done at once since this southbridge code is used for different northbridges, which fails to compile when done separately. This needs an acpi_name functions in the northbridge code to be defined. TESTED on Intel DG43GT: show correct PIRQ ACPI entries in /sys/firmware/acpi/tables/SSDT. Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/22981 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../apple/macbook21/acpi/i945_pci_irqs.asl | 66 --------------- src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl | 66 --------------- src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl | 75 ----------------- src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl | 79 ------------------ src/mainboard/getac/p470/acpi/i945_pci_irqs.asl | 82 ------------------- .../gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl | 75 ----------------- .../gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl | 72 ---------------- src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl | 81 ------------------ .../intel/d510mo/acpi/pineview_pci_irqs.asl | 72 ---------------- .../intel/d945gclf/acpi/i945_pci_irqs.asl | 81 ------------------ src/mainboard/intel/dg41wv/acpi/x4x_pci_irqs.asl | 66 --------------- src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl | 95 ---------------------- .../kontron/986lcd-m/acpi/i945_pci_irqs.asl | 81 ------------------ src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl | 58 ------------- src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl | 58 ------------- src/mainboard/lenovo/z61t/acpi/i945_pci_irqs.asl | 58 ------------- src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl | 79 ------------------ src/northbridge/intel/i945/acpi/hostbridge.asl | 3 - src/northbridge/intel/i945/northbridge.c | 18 +++- src/northbridge/intel/pineview/acpi/hostbridge.asl | 3 - src/northbridge/intel/pineview/northbridge.c | 17 ++++ src/northbridge/intel/x4x/acpi/hostbridge.asl | 3 - src/northbridge/intel/x4x/northbridge.c | 17 ++++ src/southbridge/intel/i82801gx/Kconfig | 1 + src/southbridge/intel/i82801gx/lpc.c | 13 +++ src/southbridge/intel/i82801jx/Kconfig | 1 + src/southbridge/intel/i82801jx/lpc.c | 8 ++ 27 files changed, 74 insertions(+), 1254 deletions(-) delete mode 100644 src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl delete mode 100644 src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl delete mode 100644 src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl delete mode 100644 src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl delete mode 100644 src/mainboard/getac/p470/acpi/i945_pci_irqs.asl delete mode 100644 src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl delete mode 100644 src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl delete mode 100644 src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl delete mode 100644 src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl delete mode 100644 src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl delete mode 100644 src/mainboard/intel/dg41wv/acpi/x4x_pci_irqs.asl delete mode 100644 src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl delete mode 100644 src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl delete mode 100644 src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl delete mode 100644 src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl delete mode 100644 src/mainboard/lenovo/z61t/acpi/i945_pci_irqs.asl delete mode 100644 src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl (limited to 'src') diff --git a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl deleted file mode 100644 index 5e5facbb4b..0000000000 --- a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0001FFFF, 0, 0, 0x10 }, - Package() { 0x0002FFFF, 0, 0, 0x10 }, - Package() { 0x0007FFFF, 0, 0, 0x10 }, - Package() { 0x001BFFFF, 0, 0, 0x16 }, - Package() { 0x001CFFFF, 0, 0, 0x11 }, - Package() { 0x001CFFFF, 1, 0, 0x10 }, - Package() { 0x001CFFFF, 2, 0, 0x12 }, - Package() { 0x001CFFFF, 3, 0, 0x13 }, - Package() { 0x001DFFFF, 0, 0, 0x15 }, - Package() { 0x001DFFFF, 1, 0, 0x13 }, - Package() { 0x001DFFFF, 2, 0, 0x12 }, - Package() { 0x001DFFFF, 3, 0, 0x10 }, - Package() { 0x001EFFFF, 0, 0, 0x16 }, - Package() { 0x001EFFFF, 1, 0, 0x14 }, - Package() { 0x001FFFFF, 0, 0, 0x12 }, - Package() { 0x001FFFFF, 1, 0, 0x13 }, - Package() { 0x001FFFFF, 3, 0, 0x10 } - }) - } Else { - Return (Package() { - Package() { 0x0001FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0002FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0007FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001BFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001CFFFF, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001CFFFF, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001CFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001CFFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001DFFFF, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001DFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001DFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001DFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001EFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001EFFFF, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x001FFFFF, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001FFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001FFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) - } -} diff --git a/src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl deleted file mode 100644 index 5bec150f0b..0000000000 --- a/src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for x4x */ - -/* PCI Interrupt Routing */ -Method(_PRT) -{ - If (PICM) { - Return (Package() { - /* PEG */ - Package() { 0x0001ffff, 0, 0, 0x10 }, - /* Internal GFX */ - Package() { 0x0002ffff, 0, 0, 0x10 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, 0, 0x10 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, 0, 0x10 }, - Package() { 0x001cffff, 1, 0, 0x11 }, - Package() { 0x001cffff, 2, 0, 0x12 }, - Package() { 0x001cffff, 3, 0, 0x13 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, 0, 0x17 }, - Package() { 0x001dffff, 1, 0, 0x13 }, - Package() { 0x001dffff, 2, 0, 0x12 }, - Package() { 0x001dffff, 3, 0, 0x10 }, - /* PATA/SATA/SMBUS 0:1f.1-3 */ - Package() { 0x001fffff, 0, 0, 0x12 }, - Package() { 0x001fffff, 1, 0, 0x13 }, - }) - } Else { - Return (Package() { - /* PEG */ - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* Internal GFX */ - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PATA/SATA/SMBUS 0:1f.1-3 */ - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl b/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl deleted file mode 100644 index 4aaa33fe74..0000000000 --- a/src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 16 }, - Package() { 0x001dffff, 1, 0, 17 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 19 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 16 }, - Package() { 0x001fffff, 1, 0, 17 }, - Package() { 0x001fffff, 2, 0, 18 }, - Package() { 0x001fffff, 3, 0, 19 }, - - }) - - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl b/src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl deleted file mode 100644 index bb48e88efe..0000000000 --- a/src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Arthur Heymans - * Copyright (C) 2017 Samuel Holland - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for x4x */ - -/* PCI Interrupt Routing */ -Method(_PRT) -{ - If (PICM) { - Return (Package() { - /* PEG 0:01.0 */ - Package() { 0x0001ffff, 0, 0, 0x10 }, - Package() { 0x0001ffff, 1, 0, 0x11 }, - Package() { 0x0001ffff, 2, 0, 0x12 }, - Package() { 0x0001ffff, 3, 0, 0x13 }, - /* Internal GFX 0:02.0 */ - Package() { 0x0002ffff, 0, 0, 0x10 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, 0, 0x10 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, 0, 0x10 }, - Package() { 0x001cffff, 1, 0, 0x11 }, - Package() { 0x001cffff, 2, 0, 0x12 }, - Package() { 0x001cffff, 3, 0, 0x13 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, 0, 0x17 }, - Package() { 0x001dffff, 1, 0, 0x13 }, - Package() { 0x001dffff, 2, 0, 0x12 }, - Package() { 0x001dffff, 3, 0, 0x10 }, - /* PCI Bridge 0x1e.0 */ - Package() { 0x001effff, 0, 0, 0x11 }, - Package() { 0x001effff, 1, 0, 0x14 }, - /* PATA/SATA/SMBUS 0:1f.x */ - Package() { 0x001fffff, 0, 0, 0x12 }, - Package() { 0x001fffff, 1, 0, 0x13 }, - }) - } Else { - Return (Package() { - /* PEG 0:01.0 */ - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - /* Internal GFX 0:02.0 */ - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PCI Bridge 0x1e.0 */ - Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - /* PATA/SATA/SMBUS 0:1f.x */ - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl b/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl deleted file mode 100644 index 5bbf144bfa..0000000000 --- a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Network - Package() { 0x0007ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 16 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 22 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Network 0:7.0 - Package() { 0x0007ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) - } -} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl deleted file mode 100644 index 4aaa33fe74..0000000000 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 16 }, - Package() { 0x001dffff, 1, 0, 17 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 19 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 16 }, - Package() { 0x001fffff, 1, 0, 17 }, - Package() { 0x001fffff, 2, 0, 18 }, - Package() { 0x001fffff, 3, 0, 19 }, - - }) - - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl deleted file mode 100644 index 46e8a4af5a..0000000000 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for x4x */ - -/* PCI Interrupt Routing */ -Method(_PRT) -{ - If (PICM) { - Return (Package() { - /* PEG */ - Package() { 0x0001ffff, 0, 0, 16 }, - /* Internal GFX */ - Package() { 0x0002ffff, 0, 0, 16 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, 0, 16 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 1, 0, 19 }, - }) - } Else { - Return (Package() { - /* PEG */ - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* Internal GFX */ - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl b/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl deleted file mode 100644 index 0db7bc773f..0000000000 --- a/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - Package() { 0x0001ffff, 1, 0, 17 }, - Package() { 0x0001ffff, 2, 0, 18 }, - Package() { 0x0001ffff, 3, 0, 19 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - //Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97/IDE 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 17 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19}, - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // AC97/IDE 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl deleted file mode 100644 index 3fa6fdba7d..0000000000 --- a/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for pineview */ -/* FIXME: EHCI controller not working yet */ - -/* PCI Interrupt Routing */ -Method(_PRT) -{ - If (PICM) { - Return (Package() { - /* Internal GFX */ - Package() { 0x0002ffff, 0, 0, 16 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, 0, 22 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 16 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - Package() { 0x001dffff, 0, 0, 23 }, - /* PCI 0:1e.0 */ - Package() { 0x001effff, 0, 0, 22 }, - /* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */ - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 1, 0, 19 }, - }) - } Else { - Return (Package() { - /* Internal GFX */ - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - /* PCI 0:1e.0 */ - Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - /* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */ - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl deleted file mode 100644 index a7fcc8528f..0000000000 --- a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - Package() { 0x0001ffff, 1, 0, 17 }, - Package() { 0x0001ffff, 2, 0, 18 }, - Package() { 0x0001ffff, 3, 0, 19 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 16 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 22 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19 }, - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/intel/dg41wv/acpi/x4x_pci_irqs.asl b/src/mainboard/intel/dg41wv/acpi/x4x_pci_irqs.asl deleted file mode 100644 index 5bec150f0b..0000000000 --- a/src/mainboard/intel/dg41wv/acpi/x4x_pci_irqs.asl +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for x4x */ - -/* PCI Interrupt Routing */ -Method(_PRT) -{ - If (PICM) { - Return (Package() { - /* PEG */ - Package() { 0x0001ffff, 0, 0, 0x10 }, - /* Internal GFX */ - Package() { 0x0002ffff, 0, 0, 0x10 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, 0, 0x10 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, 0, 0x10 }, - Package() { 0x001cffff, 1, 0, 0x11 }, - Package() { 0x001cffff, 2, 0, 0x12 }, - Package() { 0x001cffff, 3, 0, 0x13 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, 0, 0x17 }, - Package() { 0x001dffff, 1, 0, 0x13 }, - Package() { 0x001dffff, 2, 0, 0x12 }, - Package() { 0x001dffff, 3, 0, 0x10 }, - /* PATA/SATA/SMBUS 0:1f.1-3 */ - Package() { 0x001fffff, 0, 0, 0x12 }, - Package() { 0x001fffff, 1, 0, 0x13 }, - }) - } Else { - Return (Package() { - /* PEG */ - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* Internal GFX */ - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PATA/SATA/SMBUS 0:1f.1-3 */ - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl b/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl deleted file mode 100644 index a0e7f07d1c..0000000000 --- a/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Arthur Heymans - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for x4x */ -/* Uses reset defaults + some undocumented device taken from vendor DSDT*/ - -/* PCI Interrupt Routing */ -Method(_PRT) -{ - If (PICM) { - Return (Package() { - /* PEG */ - Package() { 0x0001ffff, 0, 0, 0x10 }, - /* Internal GFX */ - Package() { 0x0002ffff, 0, 0, 0x10 }, - /* ME */ - Package() { 0x0003ffff, 0, 0, 0x10 }, - Package() { 0x0003ffff, 1, 0, 0x11 }, - Package() { 0x0003ffff, 2, 0, 0x12 }, - /* ?? */ - Package() { 0x0016ffff, 0, 0, 0x12 }, - Package() { 0x0016ffff, 1, 0, 0x13 }, - /* GBE 0:19.0 */ - Package() { 0x0019ffff, 0, 0, 0x10 }, - /* USB and EHCI */ - Package() { 0x001affff, 0, 0, 0x10 }, - Package() { 0x001affff, 1, 0, 0x11 }, - Package() { 0x001affff, 2, 0, 0x12 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, 0, 0x10 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, 0, 0x10 }, - Package() { 0x001cffff, 1, 0, 0x11 }, - Package() { 0x001cffff, 2, 0, 0x12 }, - Package() { 0x001cffff, 3, 0, 0x13 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, 0, 0x10 }, - Package() { 0x001dffff, 1, 0, 0x11 }, - Package() { 0x001dffff, 2, 0, 0x12 }, - Package() { 0x001dffff, 3, 0, 0x13 }, - /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ - Package() { 0x001fffff, 1, 0, 0x11 }, - Package() { 0x001fffff, 2, 0, 0x12 }, - Package() { 0x001fffff, 3, 0, 0x13 }, - }) - } Else { - Return (Package() { - /* PEG */ - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* Internal GFX */ - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* ME */ - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - - Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - /* GBE */ - Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* USB */ - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - /* PATA/SATA/SMBUS 0:1f.1-3 */ - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl b/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl deleted file mode 100644 index efb94c6745..0000000000 --- a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - Package() { 0x0001ffff, 1, 0, 17 }, - Package() { 0x0001ffff, 2, 0, 18 }, - Package() { 0x0001ffff, 3, 0, 19 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97/IDE 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 17 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19}, - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // AC97/IDE 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} diff --git a/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl deleted file mode 100644 index f0d76db435..0000000000 --- a/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA - Package() { 0x001bffff, 1, 0, 0x11 }, // Audio - Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge - Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge - Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge - Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge - Package() { 0x001dffff, 0, 0, 0x10 }, // USB - Package() { 0x001dffff, 1, 0, 0x11 }, // USB - Package() { 0x001dffff, 2, 0, 0x12 }, // USB - Package() { 0x001dffff, 3, 0, 0x13 }, // USB - Package() { 0x001fffff, 0, 0, 0x17 }, // LPC - Package() { 0x001fffff, 1, 0, 0x10 }, // IDE - Package() { 0x001fffff, 2, 0, 0x10 } // SATA - }) - } Else { - Return (Package() { - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA - Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 } // SATA - }) - } -} diff --git a/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl deleted file mode 100644 index f0d76db435..0000000000 --- a/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA - Package() { 0x001bffff, 1, 0, 0x11 }, // Audio - Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge - Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge - Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge - Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge - Package() { 0x001dffff, 0, 0, 0x10 }, // USB - Package() { 0x001dffff, 1, 0, 0x11 }, // USB - Package() { 0x001dffff, 2, 0, 0x12 }, // USB - Package() { 0x001dffff, 3, 0, 0x13 }, // USB - Package() { 0x001fffff, 0, 0, 0x17 }, // LPC - Package() { 0x001fffff, 1, 0, 0x10 }, // IDE - Package() { 0x001fffff, 2, 0, 0x10 } // SATA - }) - } Else { - Return (Package() { - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA - Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 } // SATA - }) - } -} diff --git a/src/mainboard/lenovo/z61t/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/z61t/acpi/i945_pci_irqs.asl deleted file mode 100644 index f0d76db435..0000000000 --- a/src/mainboard/lenovo/z61t/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA - Package() { 0x001bffff, 1, 0, 0x11 }, // Audio - Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge - Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge - Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge - Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge - Package() { 0x001dffff, 0, 0, 0x10 }, // USB - Package() { 0x001dffff, 1, 0, 0x11 }, // USB - Package() { 0x001dffff, 2, 0, 0x12 }, // USB - Package() { 0x001dffff, 3, 0, 0x13 }, // USB - Package() { 0x001fffff, 0, 0, 0x17 }, // LPC - Package() { 0x001fffff, 1, 0, 0x10 }, // IDE - Package() { 0x001fffff, 2, 0, 0x10 } // SATA - }) - } Else { - Return (Package() { - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA - Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 } // SATA - }) - } -} diff --git a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl deleted file mode 100644 index a7d999e9c3..0000000000 --- a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * i945 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 16 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, 0, 22 }, - Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 1, 0, 20 }, - Package() { 0x001fffff, 3, 0, 16 } - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // AC97 0:1e.2, 0:1e.3 - Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } - }) - } -} diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index 5877b0e922..7b3917da97 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -228,6 +228,3 @@ Method (_CRS, 0, Serialized) Return (MCRS) } - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/i945_pci_irqs.asl" diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index b8a225562b..d3539b86e6 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -117,6 +117,22 @@ static void pci_domain_set_resources(struct device *dev) assign_resources(dev->link_list); } +static const char *northbridge_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) + return NULL; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0, 0): + return "MCHC"; + } + + return NULL; +} + /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. @@ -127,6 +143,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, + .acpi_name = northbridge_acpi_name, }; static void mc_read_resources(struct device *dev) @@ -154,7 +171,6 @@ static void intel_set_subsystem(struct device *dev, unsigned int vendor, ((device & 0xffff) << 16) | (vendor & 0xffff)); } } - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl index d759514bbf..3eff101d99 100644 --- a/src/northbridge/intel/pineview/acpi/hostbridge.asl +++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl @@ -230,6 +230,3 @@ Method (_CRS, 0, Serialized) Return (MCRS) } - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/pineview_pci_irqs.asl" diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 93c7558931..0bba03da29 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -147,12 +147,29 @@ static void mch_domain_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32); } +static const char *northbridge_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) + return NULL; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0, 0): + return "MCHC"; + } + + return NULL; +} + static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_name = northbridge_acpi_name, }; static void cpu_bus_init(struct device *dev) diff --git a/src/northbridge/intel/x4x/acpi/hostbridge.asl b/src/northbridge/intel/x4x/acpi/hostbridge.asl index 530fdfafd9..90f15c78c1 100644 --- a/src/northbridge/intel/x4x/acpi/hostbridge.asl +++ b/src/northbridge/intel/x4x/acpi/hostbridge.asl @@ -229,6 +229,3 @@ Method (_CRS, 0, Serialized) Return (MCRS) } - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/x4x_pci_irqs.asl" diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 3e5022962a..0fcc297639 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -156,6 +156,22 @@ static void mch_domain_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32); } +static const char *northbridge_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) + return NULL; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0, 0): + return "MCHC"; + } + + return NULL; +} + static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, @@ -163,6 +179,7 @@ static struct device_operations pci_domain_ops = { .scan_bus = pci_domain_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_name = northbridge_acpi_name, }; diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2670d23c9d..7e48848c7b 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -27,6 +27,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select HAVE_INTEL_CHIPSET_LOCKDOWN + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index acc57a7dfb..ac83ec9500 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "nvs.h" #define NMI_OFF 0 @@ -718,6 +719,16 @@ static void southbridge_inject_dsdt(struct device *dev) } } +static const char *lpc_acpi_name(const struct device *dev) +{ + return "LPCB"; +} + +static void southbridge_fill_ssdt(device_t device) +{ + intel_acpi_gen_def_acpi_pirq(device); +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; @@ -728,6 +739,8 @@ static struct device_operations device_ops = { .enable_resources = pci_dev_enable_resources, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, + .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_name = lpc_acpi_name, .init = lpc_init, .scan_bus = scan_lpc_bus, .enable = i82801gx_enable, diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index e418a94f60..2c98f72e4b 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801JX select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ff86f0fddd..cd5e3078b0 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -34,6 +34,7 @@ #include "i82801jx.h" #include "nvs.h" #include +#include #include #define NMI_OFF 0 @@ -720,12 +721,18 @@ static void southbridge_inject_dsdt(struct device *dev) } } +static const char *lpc_acpi_name(const struct device *dev) +{ + return "LPCB"; +} + static void southbridge_fill_ssdt(struct device *device) { struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); + intel_acpi_gen_def_acpi_pirq(device); } static struct pci_operations pci_ops = { @@ -739,6 +746,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_name = lpc_acpi_name, .init = lpc_init, .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, -- cgit v1.2.3