From ac9a905cf1e44570a27dea0afd9233b7418d9c1e Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 4 Dec 2013 11:29:46 -0600 Subject: rambi: configure the LPE audio codec clock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rambi has the LPE audio codec connected to PMC_PLT_CLK[0]. Configure it for 25MHz. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and booted. Noted message in console output. Change-Id: I11297ba951149e5831c65ca70ac7bdbbed113098 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/178781 Reviewed-by: Shawn Nematbakhsh Reviewed-on: http://review.coreboot.org/4987 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- src/mainboard/google/rambi/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 88785c0032..1c24d57d2d 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -23,6 +23,10 @@ chip soc/intel/baytrail register "usb2_per_port_lane3" = "0x00049a09" register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + device cpu_cluster 0 on device lapic 0 on end end -- cgit v1.2.3