From b0eb594b34f17ccb357c768f38d0716679e93e7f Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Sun, 23 Aug 2015 17:24:43 -0700 Subject: soc/braswell: Set max frequency to be turbo frequency In set_max_freq, instead of using ratio from IA_CORE_RATIOS, using ratio from MSR_IACORE_TURBO_RATIOS Also, punit_init needs to be called before enabling this frequency. Original-Reviewed-on: https://chromium-review.googlesource.com/295268 Original-Reviewed-by: Aaron Durbin Original-Tested-by: Hannah Williams Change-Id: Iabdab9ec45f8eef0a105a5a05dbcdb997b6764b0 Signed-off-by: Hannah Williams Reviewed-on: https://review.coreboot.org/12736 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc Reviewed-by: Martin Roth --- src/soc/intel/braswell/ramstage.c | 1 + src/soc/intel/braswell/tsc_freq.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 1e085d7e93..155c8a2e46 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -196,6 +196,7 @@ void soc_init_pre_device(struct soc_intel_braswell_config *config) /* Perform silicon specific init. */ intel_silicon_init(); + set_max_freq(); set_board_id(); /* Get GPIO initial states from mainboard */ diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index fff882eb9b..f4f1a8be8c 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -72,18 +72,23 @@ void set_max_freq(void) msr.lo |= (1 << 16); wrmsr(MSR_IA32_MISC_ENABLES, msr); + /* Enable Burst Mode */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.hi = 0; + wrmsr(MSR_IA32_MISC_ENABLES, msr); + /* * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of * the PERF_CTL. */ - msr = rdmsr(MSR_IACORE_RATIOS); + msr = rdmsr(MSR_IACORE_TURBO_RATIOS); perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; /* * Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of * the PERF_CTL. */ - msr = rdmsr(MSR_IACORE_VIDS); + msr = rdmsr(MSR_IACORE_TURBO_VIDS); perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; -- cgit v1.2.3