From b27fb330c40c318188e34606d987661de079960f Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Mon, 4 Mar 2019 08:02:43 +0100 Subject: soc/intel/braswell: Add SMBus support Intel Braswell SoC contains SMBus controller but no support is available for this controller. This controller is compatible with the Intel SMBus support in the southbridge common directory. To be able using smbus support from the Intel common directory the smbus.c is moved outside SOUTHBRIDGE_INTEL_COMMON dependency block. Use SOUTHBRIDGE_INTEL_COMMON_SMBUS to include support. BUG=N/A TEST= Facebook FBG-1710 LCD panel Change-Id: Ie3d4f657558a1aed21b083ef5cad08ea96e629c3 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/31661 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Nico Huber --- src/soc/intel/braswell/Kconfig | 1 + src/southbridge/intel/common/Makefile.inc | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 061c494987..fda5a6d687 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON + select SOUTHBRIDGE_INTEL_COMMON_SMBUS config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 3224e1fcf1..3ad79248a0 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -22,6 +22,9 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) romstage-y += pmbase.c @@ -37,9 +40,6 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c -romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c -ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c - romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c -- cgit v1.2.3