From b783d4585ff6c229ec76619c3f9666070e19359e Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 9 Aug 2013 18:59:02 -0700 Subject: exynos5420: Set SPLL to 400MHz Increase SPLL to 400MHz from 300MHz as we set SPLL as the switching parent for ARM and KFC. This value is as per recommendation of the hardware team. This is ported from https://gerrit.chromium.org/gerrit/62618 Signed-off-by: David Hendricks Change-Id: I8a5a5b957083b0b1f3e3e318fe5753cf7ae19223 Reviewed-on: https://gerrit.chromium.org/gerrit/65432 Reviewed-by: Gabe Black Tested-by: David Hendricks Commit-Queue: Gabe Black Reviewed-on: http://review.coreboot.org/4464 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/cpu/samsung/exynos5420/clock_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 07bf5d95c2..8be286dd60 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -141,7 +141,7 @@ void system_clock_init(void) /* Set SPLL */ writel(SPLL_CON1_VAL, &clk->spll_con1); - val = set_pll(0xc8, 0x2, 0x3); + val = set_pll(200, 0x3, 0x2); /* 400MHz */ writel(val, &clk->spll_con0); while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0) ; -- cgit v1.2.3